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参数资料
型号： STM32F105VCH7XXX
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
封装： ROHS COMPLIANT, LFBGA-100
文件页数： 46/90页
文件大小： 998K
代理商： STM32F105VCH7XXX
Electrical characteristics
STM32F105xx, STM32F107xx
50/90
5.3.8
PLL characteristics
The parameters given in Table 27 and Table 28 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 9.
Table 26.
Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ
Unit
tWUSLEEP
(1)
1.
The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode
Wakeup on HSI RC clock
1.8
s
tWUSTOP
(1)
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 s
3.6
s
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 s, Regulator
wakeup from LP mode time = 5 s
5.4
tWUSTDBY
(1) Wakeup from Standby mode
HSI RC wakeup time = 2 s, Regulator
wakeup from power down time = 38 s
50
s
Table 27.
PLL1 characteristics
Symbol
Parameter
Value
Unit
Min(1)
1.
Based on characterization, not tested in production.
Max(1)
fPLL_IN
PLL input clock(2)
2.
Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
812
MHz
Pulse width at high level
30
ns
fPLL_OUT
PLL multiplier output clock
48
72
MHz
fVCO_OUT
PLL VCO output
96
144
MHz
tLOCK
PLL lock time
350
s
Table 28.
PLL2 and PLL3 characteristics
Symbol
Parameter
Value
Unit
Min(1)
1.
Based on characterization, not tested in production.
Max(1)
fPLL_IN
PLL input clock(2)
2.
Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
35
MHz
Pulse width at high level
30
ns
fPLL_OUT
PLL multiplier output clock
40
74
MHz
fVCO_OUT
PLL VCO output
80
148
MHz
tLOCK
PLL lock time
350
s
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