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参数资料
型号： STM8L151G4U3
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, QCC28
封装： 4 X 4 MM, ROHS COMPLIANT, WFQFPN-28
文件页数： 80/109页
文件大小： 2050K
代理商： STM8L151G4U3
Electrical parameters
STM8L151xx, STM8L152xx
72/109
Doc ID 15962 Rev 3
Current consumption of on-chip peripherals
Table 24.
Peripheral current consumption
Symbol
Parameter
Typ.
VDD = 3.0 V
Unit
IDD(TIM1)
TIM1 supply current(1)
13
A/MHz
IDD(TIM2)
TIM2 supply current (1)
8
IDD(TIM3)
TIM3 supply current (1)
8
IDD(TIM4)
TIM4 timer supply current (1)
3
IDD(USART1)
USART1 supply current (2)
6
IDD(SPI1)
SPI1 supply current (2)
3
IDD(I2C1)
I2C1 supply current (2)
5
IDD(DMA1)
DMA1 supply current
3
IDD(WWDG)
WWDG supply current
2
IDD(ALL)
Peripherals ON(3)
44
A/MHz
IDD(RTC)
RTC supply current when clocked by LSI
TBD
A
RTC supply current when clocked at 1 MHz
TBD
IDD(LCD)
LCD supply current when clocked at 32 kHz /2
TBD
LCD supply current when clocked at 1 MHz /2
TBD
IDD(ADC1)
ADC1 supply current(4)
1500
A
IDD(DAC)
DAC supply current(5)
370
IDD(COMP1)
Comparator 1 supply current(6)
0.160
IDD(COMP2)
Comparator 2 supply current(6)
Slow mode
2
Fast mode
5
IDD(PVD/BOR)
Power voltage detector and brownout Reset unit supply current
(7)
2.8
IDD(IDWDG)
Independent watchdog supply current
TBD
1.
Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2.
Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.
3.
Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
4.
Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
5.
Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD /2. Floating DAC output.
6.
Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
7.
Including supply current of internal reference voltage.
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