参数资料
型号: STP2011PGA50
元件分类: 参考电压二极管
英文描述: Low Current Operation at 250 ,Low Reverse Leakage,Low Noise Zener Diode
中文描述: 250 的低电流运算,低反向泄露,低噪声稳压二极管
文件页数: 6/20页
文件大小: 221K
代理商: STP2011PGA50
6
STP2000QFP
32-bit SBus Master I/O Controller
Master I/O
July 1997
1. The Parallel Port control and data line direction bits, (for example, P_*_DIR), are gang programmed by the DIR bit of the Transfer
Control Register.
DIR=0 sets transfer direction away from the STP2000 (P_D_DIR=P_DS_DIR=1; P_BSY_DIR=P_ACK_DIR=0); DIR=1 sets transfer
direction towards the STP2000 (P_D_DIR=P_DS_DIR=0; P_BSY_DIR=P_ACK_DIR=1).
P_ACK
I/O
Parallel Port Acknowledge (25
μ
A pull-down)
(ELP_PE) P_PE
I/O
Parallel Port Paper Error
P_SLCT
I/O
Parallel Port Select
P_ERROR
Input
Parallel Port Error
P_INIT
Output
Parallel Port Initialize
P_SLCT_IN
Output
Parallel Port Select In
P_AFXN
P_DS_DIR
[1]
P_BSY_DIR
[1]
P_ACK_DIR
[1]
P_D_DIR
[1]
Output
Parallel Port Auto Feed
Output
Parallel Port Data Strobe Direction
Output
Parallel Port Busy Direction
Output
Parallel Port Acknowledge Direction
Output
Parallel Port Data Direction
ID_CS
Output
Secondary Device Select (boot prom) output; pull low to specify absence of external
PROM
JTAG Interface
Name
Type
Description
JTAG_TDO
Output
JTAG Test Data Output
JTAG_TDI
Input
JTAG Test Data Input (100
μ
A pull-up)
JTAG_CLK
Input
JTAG Clock
JTAG_TMS
Input
JTAG Test Mode Select (100
μ
A pull-up)
JTAG Reset (100
μ
A pull-up)
JTAG_RST
Input
Clock/Oscillator Interface
[1]
Name
Type
Description
SCC_20_IN
Input
SCC Clock Crystal In (19.66 MHz) (can drive with external CMOS clock)
SCC_20_OUT
Output
SCC Clock Crystal Out (19.66 MHz) (must not connect to any external load)
SCC_CLK20
Output
SCC Clock Out (19.66 MHz)
FPY_24_IN
Input
Floppy Clock Crystal In (24 MHz) (can drive with external CMOS clock)
FPY_24_OUT
Output
Floppy Clock Crystal Out (24 MHz) (must not connect to any external load)
FPY_CLK24
Output
Floppy Clock Out (24 MHz)
Parallel Port Interface
Name
Type
Description
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