20

July 1997Basic Memory TimingThe memory controller (MC) timing is programmable so that memory timing can be optimized for differentfrequencies. Memory refresh and access timing have been divided into a number of segments. Memory Con-trol and Status Register 1 (MCSR1) contains seven elds which allow custom tailoring of any particularsegment: WPC1, RCD, PC0, CP, PC1, RP, and

RAS. For a detailed description of these elds, see the program-ming model described in the USC User Manual.The timing diagram inFigure 20 shows a generic template for a read or write transaction, how it is brokendown into segments, and the corresponding elds in MCSR1 which control the width of each segment. Eachindividual segment is programmable by the rmware to optimize memory timing. See Figure 4 2through Fig-ure 483for default memory timings.Figure 40. Basic Read/Write Timing1. RCD is the

RAS-to-

CAS delay.2. PC0 is the page cycle 0 time.3. CP is the

CAS-precharge time.4. PC1 is the page cycle 1 time for a read operation.5. WPC1 is the page cycle 1 time for a write operation.6. RP is the

RAS-precharge time.Note:Reads use RCD, PC0, CP, PC1, and RP. Writes only use RCD, CP, WPC1, and RP; PC0 is fixed.Figure 21 shows a generic template for a refresh operation.

RAS

CASRCD

PC0

CP

PC1/WPC1RP