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| 型号： | STPCI2EEYC |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA516 |
| 封装： | PLASTIC, BGA-516 |
| 文件页数： | 64/80页 |
| 文件大小： | 854K |
| 代理商： | STPCI2EEYC |
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BOARD LAYOUT
67/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
5.3.8 Data Mask (DQM[7:0])
The data mask load is quite similar to that of the
data signals.
5.3.9 Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For applica-
tions where speed is not so critical series termina-
tion can be used as this will save power. Using a
low impedance such as 50
for these critical trac-
es is recommended as it both reduces the delay
and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals for
unbuffered DIMMs. When using registered DIMMs
the other signals will probably be just as critical as
the address/control signals so to gain maximum
benefit from using registered DIMMs the timings
should also be considered in that situation. Using
lower impedance traces is also beneficial for the
other signals but if their timing is not as critical as
the address/control signals they could use the de-
fault value. Using a lower impedance implies us-
ing wider traces which may have an impact on the
routing of the board.
5.4 SDRAM LAYOUT EXAMPLES
The STPC provides MA, RAS#, CAS#, WE#, CS#,
DQM#, BA0 (MA[11])and MD for SDRAM control.
From 2 to 128 MBytes of main memory are sup-
ported in 1 to 4 banks. All Banks must be 64 bits
wide.
The following memory devices are supported:
4Mbit x 4, 8Mbit x 2 & 16Mbit x 1 or if in the case of
two internal bank chips, 2Mbit x 4 x 2, 4Mbit x 2 x
2 & 8Mbit x 1 x 2.
The following Figure 5-17 and Figure 5-18, shows
two possible SDRAM organizations based on one
or two bank configurations.
Notes for Figure 5-17 and Figure 5-18;
All buffers must be low skew clock buffers
One clock driver can operate up to four memory
chips.
All the clock lines must follow the rules below;
MCLKI = MCLK0 + MCLK0A
=......
= MCLK0 + MCLK0D
= MCLK1 + MCLK1A
=......
= MCLK1 + MCLK1D
This means that all line lengths must go from the
buffer to the memory chips (MCLK1 or MCLK0
or...) and from the buffer to the STPC (MCLKI)
must be identical.
5.4.1 Host Address to MA Bus Mapping
Graphics memory resides at the beginning of
Bank 0. Host memory begins at the top of graphics
memory and extends to the top of populated
SDRAM.
The bank attributes can be retrieved from a lookup
table to select the final SDRAM row and column
address mappings. (Table 5-2). Table 5-1 shows
the Standard DIMM Pinout for users wishing to de-
sign with DIMMs.
.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| STPCI2GDY | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:X86 Core PC Compatible System-on-Chip for Terminals |
| STPCI2GDYI | 功能描述:微处理器 - MPU 120MHz x86 SoC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| STPCI2GDYIE | 制造商:STMicroelectronics 功能描述: |
| STPCI2HDYC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PERIPHERAL (MULTIFUNCTION) CONTROLLER |
| STPCI2HEYC | 功能描述:微处理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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