参数资料
型号: STR912FAW44X6T
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 96 MHz, RISC MICROCONTROLLER, PQFP128
封装: 14 X 14 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, LQFP-128
文件页数: 27/100页
文件大小: 1801K
代理商: STR912FAW44X6T
Functional overview
STR91xFAxxx
and the Message SRAM, handling of transmission requests, and interrupt generation. The
CPU has access to the Message SRAM via the Message Handler using a set of 38 control
registers.
The follow features are supported by the CAN interface:
Bit rates up to 1 Mbps
Disable Automatic Retransmission mode for Time Triggered CAN applications
32 Message Objects
Each Message Object has its own Identifier Mask
Programmable FIFO mode
Programmable loopback mode for self-test operation
The CAN interface is not supported by DMA.
3.20
UART interfaces with DMA
The STR91xFA supports three independent UART serial interfaces, designated UART0,
UART1, and UART2. Each interface is very similar to the industry-standard 16C550 UART
device. All three UART channels support IrDA encoding/decoding, requiring only an external
LED transceiver to pins UARTx_RX and UARTx_Tx for communication. One UART channel
(UART0) supports full modem control signals.
UART interfaces include the following features:
Maximum baud rate of 1.5 Mbps
Separate FIFOs for transmit and receive, each 16 deep, each FIFO can be disabled by
firmware if desired
Programmable FIFO trigger levels between 1/8 and 7/8
Programmable baud rate generator based on CCU master clock, or CCU master clock
divided by two
Programmable serial data lengths of 5, 6, 7, or 8 bits with start bit and 1 or 2 stop bits
Programmable selection of even, odd, or no-parity bit generation and detection
False start-bit detection
Line break generation and detection
Support of IrDA SIR ENDEC functions for data rates of up to 115.2K bps
IrDA bit duration selection of 3/16 or low-power (1.14 to 2.23 sec)
Channel UART0 supports modem control functions CTS, DCD, DSR, RTS, DTR, and
RI
For your reference, only two standard 16550 UART features are not supported, 1.5 stop bits
and independent receive clock.
3.20.1
DMA
A programmable DMA channel may be assigned by CPU firmware to service channels
UART0 and UART1 for fast and direct transfers between the UART bus and SRAM with little
CPU involvement. Both DMA single-transfers and DMA burst-transfers are supported for
transmit and receive. Burst transfers require that UART FIFOs are enabled.
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