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参数资料
| 型号： | STVA16857AGLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | 6.10 MM WIDTH, 0.50 MM PITCH, MO-153, LEAD FREE, TSSOP-48 |
| 文件页数： | 10/13页 |
| 文件大小： | 126K |
| 代理商： | STVA16857AGLF |
6
ICSSSTVA16857
0932A—05/12/04
DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
VDDQ
MIN
TYP
MAX
UNITS
VIK
II = -18mA
2.5V
-1.2
IOH = -100A
2.5V-2.7V
VDDQ -
0.2
IOH = -8mA
2.7V
1.95
IOL = 100A
2.5V-2.7V
0.2
IOL = 8mA
2.5V
0.35
II
All Inputs
VI = VDD or GND
2.7V
±5
A
Standby (Static)
RESET# = GND
0.01
A
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
25
mA
Dynamic operating
(clock only)
RESET# = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK# switching
50% duty cycle.
30
/clock
MHz
Dynamic Operating
(per each data input)
RESET# = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
10
A/ clock
MHz/data
rOH
Output High
2.5V-2.7V
7
13.5
20
rOL
Output Low
2.5V-2.7V
7
13
20
rO(D)
[rOH - rOL] each
separate bit
2.6V
4
Data Inputs
2.5
3.5
CLK and CLK#
2.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
IO = 0
CONDITIONS
2.7V
2.6V
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
pF
IOH = -16mA
V
Ci
IOL = 16mA
IO = 20mA, TA = 25° C
VOH
VOL
IDD
IDDD
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