● Updated fast regional clock networks description on page 2–73.

● Deleted the word preliminary from the “specification for the maximum 

time to relock is 100 μs” on page 2–90.

● Added information about differential SSTL and HSTL outputs in 

“External Clock Outputs” on page 2–92.

● Updated notes in Figure 2–55 on page 2–93.

● Added information about m counter to “Clock Multiplication & 

Division” on page 2–101.

● Updated Note 1 in Table 2–58 on page 2–101.

● Updated description of “Clock Multiplication & Division” on 

page 2–88.

● Updated Table 2–22 on page 2–102.

● Added references to AN 349 and AN 329 to “External RAM 

Interfacing” on page 2–115.

● Table 2–25 on page 2–116: updated the table, updated Notes 3 and 

4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively.

● Updated Table 2–26 on page 2–117.

● Added information about PCI Compliance to page 2–120.

● Table 2–32 on page 2–126: updated the table and deleted Note 1.

● Updated reference to device pin-outs now being available on the web 

on page 2–130.

● Added Notes 4 and 5 to Table 2–36 on page 2–130.

● Updated Note 3 in Table 2–37 on page 2–131.

● Updated Note 5 in Table 2–41 on page 2–135.

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