参数资料
型号: SX1212IWLTRT
厂商: Semtech
文件页数: 31/77页
文件大小: 0K
描述: IC TXRX 300MHZ-510MHZ 32-TQFN
标准包装: 1
频率: 300MHz ~ 510MHz
数据传输率 - 最大: 150kbps
调制或协议: FSK,OOK
应用: AMR,ISM,家庭自动化,程序控制
功率 - 输出: 12.5dBm
灵敏度: -110dBm
电源电压: 2.1 V ~ 3.6 V
电流 - 接收: 3mA
电流 - 传输: 25mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-TQFN
包装: 标准包装
产品目录页面: 584 (CN2011-ZH PDF)
其它名称: SX1212IWLDKR
SX1212
ADVANCED COMMUNICATIONS & SENSING
3.4.10.3. Alternative OOK Demodulator Threshold Modes
In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold
detectors:
Fixed threshold: The value is selected through the MCParam_OOK_floor_thresh register (refer to section
3.4.10.1 for further information concerning optimization of the floor threshold).
Average threshold: Data supplied by the RSSI block is averaged with the following cutoff frequency:
RXParam _ OOK _ cutoff = 00 ? Fcutoff =
BR
8 * π
RXParam _ OOK _ cutoff = 11 ? Fcutoff =
BR
32 * π
In the first example, the higher cut-off frequency enables a sequence of up to 8 consecutive “0” or “1” to be
supported, whilst the lower cut-off frequency presented in the second example allows for the correct reception of up
to 32 consecutive “0” or “1”.
3.4.11. Bit Synchronizer
The Bit Synchronizer (BitSync) is a block that provides a clean and synchronized digital output, free of glitches.
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output
To pin DATA and
DCLK in continuous
mode
DCLK
IRQ_1
Figure 24: BitSync Description
The BitSync can be disabled through the bits RXParam_Bitsync_off, and by holding pin IRQ1 low. However, for
optimum receiver performance, its use when running Continuous mode is strongly advised. With this option a
DCLK signal is present on pin IRQ_1.
The BitSync is automatically activated in Buffered and Packet modes. The bit synchronizer bit-rate is controlled by
MCParam_BR. For a given bit rate, this parameter is determined by:
BR =
F XTAL
64 * [ 1 + MCParam _ BR ]
Rev 2 – June 18th, 2009
Page 31 of 77
www.semtech.com
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