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参数资料
| 型号： | SX1223SK915 |
| 厂商： | Semtech |
| 文件页数： | 15/25页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER FOR XE1223 915MHZ |
| 产品培训模块： | SX1223 ISM Transmitter |
| 标准包装： | 1 |
| 类型： | 发射器，UHF |
| 频率： | 915MHz |
| 适用于相关产品： | XE1223（915MHz） |
| 已供物品： | 2 个板，2 个模块，2 根天线，线缆，文档 |
| 产品目录页面： | 584 (CN2011-ZH PDF) |
SX1223
5
SERIAL INTERFACE DEFINITION AND PRINCIPLES OF OPERATION
5.1 SERIAL CONTROL INTERFACE
A 3-wire bi-directional bus (SCK, SI, SO) is used to communicate with SX1223 and gives access to the
configuration register. SCK and SI are input signals supplied externally, for example by the microcontroller. The
SX1223 configures the SO signal as an output pin during read operation, and it is tri-stated in other modes. The
falling edge of the SCK signal is used to sample the SI pin to write data into the internal shift register of the SX1223.
The rising edge of the SCK signal is used to output data by the SX1223 to the SO pin, so the microcontroller should
sample data at the falling edge of SCK. Be aware that reading data on SO output is forbidden whilst in transmit
mode.
The signal EN must be low during the whole write and read sequences. In write mode the actual content of the
configuration register is updated at the rising edge of the EN signal. Before this, the new data is stored in temporary
registers whose content does not affect the transceiver settings.
The timing diagram of a write sequence is given in Figure 7 below. The sequence is initiated when a Start condition
is detected, that is when the SI signal is set to “0” during a period of SCK. The next bit is a read/write (R/W) bit
which should be “0” to indicate a write operation. The next 5 bits are the address of the control register A[4:0] to be
accessed, MSB first. Then, the next 8 bits are the data to be written in the register. The data on SI should change at
the rising edges of SCK, and is sampled at the falling edge of SCK. The SI line should be at “1” for at least one
clock cycle on SCK before a new write or read sequence can start. In doing this, users can do multiple registers
write without a rising EN signal in between. The duty cycle of SCK must be between 40% and 60% and the
maximum frequency of this signal is 1 MHz. Over the operating supply and temperature range, set-up and hold time
for SI on the falling edge of SCK are 200ns.
SCK
SI
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
EN
SO
HZ
Figure 7: Write sequence into configuration register
The time diagram of a read sequence is given in figure below. The sequence is initiated when a Start condition is
detected, that is when the SI signal is set to “0” during a period of SCK. The next bit is a read/write (R/W) bit which
should be “1” to indicate a read operation. The next 5 bits are the address of the control register A[4:0] to be
accessed, MSB first. Then the data from the register are transmitted on the SO pin. The data become valid at the
rising edges of SCK and should be sampled at the falling edge of SCK. After this, the data transfer is terminated.
The SI line must stay high for at least one clock cycle on SCK to start a new write or read sequence. The typical
current drive on SO is 2mA @ 2.7V, the maximum load is CLop.
When the serial interface is not used for read or write operations, both SCK and SI should be set to “1”. Except in
read mode, SO is set to “HZ”.
? Semtech 2007
15
www.semtech.com
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