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参数资料
型号： SY100EP195VTCTR
厂商： MICREL INC
元件分类： 延迟线
英文描述： ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32
封装： TQFP-32
文件页数： 16/18页
文件大小： 249K
代理商： SY100EP195VTCTR
7
ECL Pro
SY100EP195V
Micrel
AC ELECTRICAL CHARACTERISTICS
V
CC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = –3.0 to –5.5V; TA = –40°C to +85°C, Notes 1, 2, 3
TA = –40
°CTA = +25°CTA = +85°C
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Frequency, Note 4
2.5
GHz
tPLH
Propagation Delay
tPHL
IN to Q; D[0-10]=0
1650
2000
2450
1800
2050
2600
1950
2250
2750
ps
IN to Q; D[0-10]=1023
9500
11500
13500
9800
12200
14000
10600
13300
15800
ps
/EN to Q: D[0-10]=0
1600
2150
2600
1800
2300
2800
2000
2500
3000
ps
D10 to CASCADE
300
420
500
325
450
550
325
525
625
ps
tRANGE
Programmable Range
tPD(max)-tPD(min)
7850
9450
8200
10000
8850
10950
ps
t
Step Delay, Note 5
D0 High
9
10
ps
D1 High
25
26
27
ps
D2 High
42
43
ps
D3 High
75
80
81
ps
D4 High
142
143
150
ps
D5 High
296
300
310
ps
D6 High
532
540
565
ps
D7 High
1080
1095
1140
ps
D8 High
2100
2150
2250
ps
D9 High
4250
4300
4500
ps
Lin
Linearity
25
tSKEW
Duty Cycle Skew, Note 6
tPHL-tPLH
25
ps
tS
Setup Time
D to LEN
200
0
200
0
200
0
ps
D to IN, Note 7
300
140
300
160
300
180
ps
/EN to IN, Note 8
300
150
300
170
300
180
ps
tH
Hold Time
LEN to D
200
60
200
100
200
80
ps
IN to /EN, Note 9
400
250
400
280
400
300
ps
tR
Release Time
/EN to IN, Note 10
500
ps
SETMAX to LEN
400
200
400
250
400
300
ps
SETMIN to LEN
350
275
350
200
350
335
ps
tJIT
Cycle-to-Cycle Jitter, Note 11
0.2
< 1
0.2
< 1
0.2
< 1
ps rms
VPP
Input Voltage Swing (Differential)
150
800
1200
150
800
1200
150
800
1200
mV
tr
Output Rise/Fall Time
tf
20% to 80% (Q)
180
250
210
300
230
325
ps
20% to 80% (CASCADE)
180
250
210
300
230
325
ps
Note 1.
AC characteristics are guaranteed by design and characterization.
Note 2.
Measured using 750mV source, 50% duty cycle clock source.
Note 3.
Tested using environment of Figure 6.
Note 4.
Refer to “Typical Operating Characteristics” for output swing performance.
Note 5.
The delays of the individual bits are cumulative.
Note 6.
Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the correspond-
ing output edge.
Note 7.
Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that
edge.
Note 8.
Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than
±75mV
to that IN, /IN transition.
Note 9.
Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response
greater than
±75mV to that IN, /IN transition.
Note 10. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
Note 11. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any
frequency between 0.0 and 2.5GHz.
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