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参数资料
| 型号： | SY100EP195VTCTR |
| 厂商： | MICREL INC |
| 元件分类： | 延迟线 |
| 英文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封装： | TQFP-32 |
| 文件页数： | 7/18页 |
| 文件大小： | 249K |
| 代理商： | SY100EP195VTCTR |
15
ECL Pro
SY100EP195V
Micrel
For best performance, use good high frequency layout
techniques, filter V
CC supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP195V data inputs and outputs.
V
BB Supply
The V
BB pin is an internally generated supply, and is
available for use only by the SY100EP195V. When unused,
this pin should be left unconnected. The two common uses
for V
BB are to handle a single-ended PECL input, and to re-
bias inputs for AC coupling applications.
If IN, /IN is driven by a single-ended output, V
BB is used
to bias the unused input. Please refer to Figures 7. The
PECL signal driving SY100EP195V may optionally be
inverted in this case.
When the signal is AC coupled, V
BB is used, as shown in
Figure 8, to re-bias IN, /IN. This ensures that SY100EP195V
inputs are within its acceptable common mode range.
In all cases, V
BB current sinking our sourcing must be
limited to 0.5mA or less.
APPLICATIONS INFORMATION
IN
/IN
Q
/Q
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
#2
#1
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (11bits)
Figure 10a. Cascading Two SY100EP195V
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP195V
#3
#2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
#1
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 10b. Cascading Three SY100EP195V
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP195V V
EE supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect V
CF and
V
EF for all possible cases.
Cascading
Two or more SY100EP195V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP195V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP195V. Using this internal circuitry, SY100EP195V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP195V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY100EP195VTG | 功能描述:延迟线/计时元素 3.3V/5V 2.5 GHz Programmable Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| SY100EP195VTG TR | 功能描述:延迟线/计时元素 3.3V/5V 2.5 GHz Programmable Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| SY100EP195VTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100EP, ECL Pro® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100EP195VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100EP, ECL Pro® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100EP196VTG | 功能描述:延迟线/计时元素 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
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