参数资料
| 型号： | SY100EP196VTG TR |
| 厂商： | Micrel Inc |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 标准包装： | 1,000 |
| 系列： | 100EP, ECL Pro® |
| 标片/步级数： | 1024 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 2.05ns |
| 接头增量： | 10ps |
| 可用的总延迟： | 2.05ns ~ 12.2ns |
| 独立延迟数： | 1 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY100EP196VTGTR SY100EP196VTGTR-ND |
3
ECL Pro
SY100EP196V
Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
D[0:9]
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
30, 31, 32, 1, 2
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
4, 5
IN, /IN
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6
VBB
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias AC-
coupled inputs to IN and /IN. When used, de-couple this pin to VCC through an 0.01F
capacitor. Limit current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the
“Digital
Control Logic Standard” section of the “Functional Description” to interface the D inputs to
CMOS or TTL.
8
VCF
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28
VEE
Most Negative Supply. Supply ground for PECL systems.
10
LEN
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
SETMIN
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12
SETMAX
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22
VCC
Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1F and
0.01F low ESR capacitors.
14, 15
CASCADE,
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
17
FTUNE
Voltage Control Input: By varying the voltage at this pin from VCC through VEE, the delay
may be fine tuned by approximately ±15ps. Leave pin floating if not used.
20, 21
Q, /Q
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
PIN DESCRIPTION
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| SY100EP196VTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100EP, ECL Pro® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100EP196VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100EP, ECL Pro® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100EP210UTG | 功能描述:缓冲器和线路驱动器 2.5-5V Dual 1:5 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SY100EP210UTG TR | 功能描述:缓冲器和线路驱动器 2.5-5V Dual 1:5 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SY100EP210UTI | 功能描述:IC CLOCK BUFFER 1:5 3GHZ 32-TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:100EP, Precision Edge® 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
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