参数资料
型号: SY58621LMG TR
厂商: Micrel Inc
文件页数: 4/20页
文件大小: 0K
描述: TXRX 3.2GBPS CML/LVPECL 24-MLF
标准包装: 1,000
系列: SY58
逻辑类型: CML/LVPECL 背板收发器,带集成环回
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘,24-MLF?
供应商设备封装: 24-MLF?(4x4)
包装: 带卷 (TR)
其它名称: SY58621LMGTR
SY58621LMGTR-ND
Micrel, Inc.
SY89465U
August 2010
M9999-080510-C
hbwhelp@micrel.com or (408) 955-1690
12
Case #4: Input Clock Failure:
Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE-enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (VIN) minimum
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur either following Case #2 or Case #3,
depending upon the last valid state at the CLK1.
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend upon rise and fall time of the input signal
and on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
Timing Diagram 4
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