参数资料
| 型号： | SY605JC TR |
| 厂商： | Micrel Inc |
| 文件页数： | 1/8页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 255TAP 28-PLCC |
| 标准包装： | 750 |
| 标片/步级数： | 255 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 4ns |
| 接头增量： | 15.7ps |
| 可用的总延迟： | 4ns ~ 40ns |
| 独立延迟数： | 1 |
| 电源电压： | 4.2 V ~ 5.7 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC |
| 包装： | 带卷 (TR) |
| 其它名称： | SY605JCTR SY605JCTR-ND |
Rev.: E
Amendment: /0
Issue Date:
May, 1998
125MHz WRITE
PROGRAMMABLE
TIMING EDGE VERNIER
SY605
FINAL
DESCRIPTION
FEATURES
Micrel-Synergy's SY605 is an ECL-compatible timing vernier
(delay generator) whose time delay is programmed via an 8-
bit code which is loaded via an independent "WRITE" input.
The SY605 is fabricated in Micrel-Synergy's proprietary
ASSET bipolar process.
This device can be retriggered at speeds up to 125MHz,
with a delay span as short as 4ns. At minimum span, the
resolution is 4ns/255 = 15.7ps per step. The delay span is
externally adjustable up to 40ns. The SY605 employs
differential TRIGGER and WRITE inputs, and produces a
differential OUTPUT pulse; all other control signals are single-
ended ECL. Edge delay is specified by an 8-bit input which is
loaded into the device with the WRITE signal. The output
pulse width will typically be 3.5ns.
The SY605 is commonly used in Automatic Test Equipment
to provide precise timing edge placement; it is also found in
many instrumentation and communications applications.
Micrel-Synergy's circuit design techniques coupled with
ASSET technology result in not only ultra-fast performance,
but allow device operation at lower power dissipation than
competing technologies. Outstanding reliability is achieved in
volume production.
s True 125MHz retrigger rate
s Pin-compatible with Bt605
s 15ps delay resolution
s Less than
± 1 LSB timing accuracy
s Differential TRIGGER and delay WRITE inputs
s Delay spans from 4 to 40ns
s Compatible with 10KH ECL logic
s Lower power dissipation 350mW typical
s Available in 28-pin plastic (PLCC) or metal (MLCC)
J-lead package
PIN CONFIGURATION
BLOCK DIAGRAM
LATCH
8
+
–
LINEAR
RAMP
GENERATOR
D
R
FF
0 = STOP
1 = RUN
OUT
IEXT
D0 - D7
WRITE
CE
TRIG
VBB
PULSE
GEN
DAC
I/V
OUT
V
CC
V
CC
NC
OUT
NC
D0
TRIG
V
EE0
WRITE
D
7
V
EE1
NC
CE
COMP1
WRITE
COMP2
NC
VBB
V
CC
TRIG
D1
D2
D3
D4
D5
D6
18
17
16
15
14
13
12
56
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23
21 20 19
22
IEXT
1
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