参数资料
型号: SY69753LHI TR
厂商: Micrel Inc
文件页数: 1/13页
文件大小: 0K
描述: IC CLOCK/DATA RECVRY 3.3V 32TQFP
标准包装: 1,000
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
主要目的: 以太网,SONET/SDH,ATM OC-3
输入: PECL
输出: PECL
电路数: 1
比率 - 输入:输出: 1:3
差分 - 输入:输出: 是/是
频率 - 最大: 155Mbps
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP 裸露焊盘
供应商设备封装: 32-EPAD-TQFP
包装: 带卷 (TR)
其它名称: SY69753LHITR
SY69753LHITR-ND
SY69753L
3.3V, 125Mbps, 155Mbps Clock
and Data Recovery
Use lower-power SY69753AL for new designs
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
December 2007
M9999-120307-F
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY69753L is a complete Clock Recovery and Data
Retiming integrated circuit for OC-3/STS-3 applications
at 155Mbps NRZ. The device is ideally suited for
SONET/SDH/ATM applications and other high-speed
data transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY69753L also includes a link fault detection circuit.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
3.3V power supply
SONET/SDH/ATM compatible
Clock and data recovery for 125Mbps/155Mbps NRZ
data stream
Two on-chip PLLs: one for clock generation and
another for clock recovery
Selectable reference frequencies
Differential PECL high-speed serial I/O
Line receiver input: no external buffering needed
Link fault indication
100k ECL compatible I/O
Industrial temperature range (–40°C to +85°C)
Complies with Bellcore, ITU/CCITT and ANSI
specifications for OC-3 applications
Available in 32-pin EPAD-TQFP
Applications
Ethernet media converter(m)
SONET/SDH/ATM OC-3
Proprietary architecture at 135Mbps to 180Mbps
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