参数资料
型号: SY69753LHI TR
厂商: Micrel Inc
文件页数: 12/13页
文件大小: 0K
描述: IC CLOCK/DATA RECVRY 3.3V 32TQFP
标准包装: 1,000
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
主要目的: 以太网,SONET/SDH,ATM OC-3
输入: PECL
输出: PECL
电路数: 1
比率 - 输入:输出: 1:3
差分 - 输入:输出: 是/是
频率 - 最大: 155Mbps
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP 裸露焊盘
供应商设备封装: 32-EPAD-TQFP
包装: 带卷 (TR)
其它名称: SY69753LHITR
SY69753LHITR-ND
MCP7940M
DS22292A-page 8
Preliminary
2012 Microchip Technology Inc.
FIGURE 3-2:
ACKNOWLEDGE TIMING
3.1.2
DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’. The RTCC registers and
the SRAM share the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The next byte received defines the address of
the data byte (Figure 3-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7940M monitors
the SDA bus, checking the device type identifier being
transmitted. Upon receiving a ‘1101111’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
MCP7940M will select a read or write operation.
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
SCL
9
8
7
6
5
4
3
2
11
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
1
101
R/W
X
A
0
SRAM RTCC CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
111
X = Don’t Care
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