参数资料
| 型号： | SY87721LHY TR |
| 厂商： | Micrel Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 64-TQFP |
| 标准包装： | 1,000 |
| 系列： | AnyRate® |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，ATM 应用 |
| 输入： | PECL |
| 输出： | CML，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | SY87721LHYTR SY87721LHYTR-ND |
SY87721L
5
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
DIVSEL1, ..., DIVSEL3 [Divider Select] – TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 4. Please note that the divide by 32
selection, “011”, is only available for use when FREQSEL
are set to “000.”
REFCLK
DIVSEL1
DIVSEL2
DIVSEL3
Multiplier
00
0
1
00
1
2
01
0
4
01
1
32
10
0
8
10
1
10
11
0
16
11
1
20
Table 2(1). Reference Clock Multiplier Truth Table
Note:
1. Some combinations of FREQSEL and DIVSEL result in undefined behavior.
Refer to Table 3 for more details.
CLKSEL [Clock Select] – TTL Input
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs. Do not use for skew matching.
ENPECL [Enable ECL] – TTL Input
This input, when HIGH (ENPECL = 1), enables the
differential PECL outputs TCLKE
±, RDOUTE±, and RCLKE±.
It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,
RDOUTC–, and RCLKC– logic LOW.
When set LOW (ENPECL = 0), this signal enables the
differential CML outputs TCLKC
±, RDOUTC±, and RCLKC±.
It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,
RDOUTE– and RCLKE– logic LOW.
ALRSEL [Auto Lock Range Select] – TTL Input
This pin defines the frequency difference, and the
frequency difference hysteresis at which ‘in-lock’ and ‘out of
lock’ conditions are declared. Please refer to the “AC
Characteristics” for more details.
PIN NAMES
INPUTS
BRDMX [BRD Mux] – PECL Input
This signal indicates what data appears at the BRD
±
output. When logic HIGH, BRD
± is a direct copy of what
appears at RDOUTC
±. When logic low, BRD± is a copy of
what appears at RDIN
±. Unlike RDOUTC±, BRD± conveys
valid data even when ENPECL is logic LOW. Please refer
to Table 1.
BRDMX (Input)
BRD
± (Output)
0
RDIN
±
1
RDOUTC
±
Table 1. BRDMX Truth Table
RDIN
± [Serial Data Input] – Differential PECL Input
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75K
resistor tied to V
CC.
REFCLK
± [Reference Clock] – Differential PECL Input
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 340MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75K
resistor tied to V
CC.
CD [Carrier Detect] – PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDOUT output will be internally forced to a
constant LOW, the Link Fault Indicator output LFIN forced
LOW, and the clock recovery PLL forced to lock onto the
synthesized clock frequency generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select] – TTL Inputs
These inputs select the output clock frequency range via
either one of three PLLs, or a SONET/SDH specific PLL.
Only the selected PLL is enabled. All other PLLs are
disabled. Refer to Table 3 for more details.
FREQSEL1, ..., FREQSEL3 [Frequency Select] – TTL Inputs
These inputs select the post divide ratio of the VCO.
Refer to Table 3 for more details.
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相关代理商/技术参数 |
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| SY87724L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
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