参数资料
| 型号： | SY87721LHY TR |
| 厂商： | Micrel Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 64-TQFP |
| 标准包装： | 1,000 |
| 系列： | AnyRate® |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，ATM 应用 |
| 输入： | PECL |
| 输出： | CML，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | SY87721LHYTR SY87721LHYTR-ND |
SY87721L
6
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
OUTPUTS
BRD
± [Buffered Recovered Data] – Differential CML Output
The signal is either a buffered RDIN
± or RDOUTC±,
depending on the state of the BRDMX input. This allows a
user to selectively bypass the CDR or not, as warranted by
architecture. This CML output has a voltage swing of 400mV
loaded.
LFIN [Link Fault Indicate] – O.C. TTL Output
This output indicates the status of the input data stream
RDIN. Active HIGH indicates that the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range
of the Receive PLL (as per ALRSEL). LFIN is an
asynchronous output.
RDOUTE
± [Receive Data Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered data from the input data stream (RDIN). It is
specified on the rising edge of RCLK.
RDOUTC
± [Receive Data Out] – Differential CML Output
This is the CML version of RDOUTE
±.
RCLKE
± [Receive Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered clock used to sample the recovered data
(RDOUT).
RCLKC
± [Receive Clock Out] – Differential CML Output
This is the CML version of RCLKE
±.
TCLKE
± [Transmit Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
either the recovered clock (CLKSEL = HIGH) used to sample
the recovered data (RDOUT) or the transmit clock of the
frequency synthesizer (CLKSEL = LOW).
TCLKC
± [Transmit Clock Out] – Differential CML Output
This is the CML version of TCLKE
±.
PLLSN+, PLLSN– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis narrow
band PLL.
PLLSW+, PLLSW– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis wide band
PLL.
PLLRN+, PLLRN– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery narrow
band PLL.
PLLRW+, PLLRW– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery wide band
PLL.
OTHERS
VCC
Supply Voltage
VCCO
Output Supply Voltage
VCCA
Analog Supply Voltage
GND
Ground
GNDA
Analog Ground
NC
These pins are for factory test, and are to be
left unconnected during normal use.
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相关代理商/技术参数 |
参数描述 |
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| SY87724L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724L_06 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724L_08 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724LE | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V AnyRate?? MUX/DEMUX Up to 2.7GHz |
| SY87724LH1 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
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