参数资料
| 型号： | SY89297UMG TR |
| 厂商： | Micrel Inc |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 24-QFN |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 标片/步级数： | 1024 |
| 功能： | 多重，可编程 |
| 延迟到第一抽头： | 2ns |
| 接头增量： | 5ps |
| 可用的总延迟： | 2ns ~ 7.5ns |
| 独立延迟数： | 2 |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
Micrel, Inc.
SY89297U
December 2011
7
M9999-120211-C
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics(7)
TA = 40°C to +85°C, Channels A and B, unless otherwise stated.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Δt
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
D0-D9 High
5
10
20
40
80
160
320
640
1280
2560
5115
ps
Monotonic
5
25
INL
Integral Non-Linearity
Note 9
15
+15
ps
tS
Setup Time
SDATA to SCLK
SCLK to SLOAD
/EN to IN
Note 10
Note 11
400
300
ps
tH
Hold Time
SLOAD to SCLK
IN to /EN
SCLK to SDATA
Note 12
Note 13
300
100
200
ps
tPW
Pulse Width
SLOAD
1000
ps
tR
Release Time
/EN to IN
Note 14
800
ps
tJITTER
Cycle-to-Cycle Jitter
Total Jitter
Random Jitter
Note 15
Note 16
Note 17
2
20
2
psRMS
psPP
psRMS
tr, tf
Output Rise/Fall Time
20% to 80% (Q)
30
55
80
ps
Duty Cycle
Input Frequency = 1.6GHz
45
55
%
Notes:
7.
High frequency AC electricals are guaranteed by design and characterization.
8.
Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output.
9.
INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The
maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1023. INL = measured
delay – (measured minimum delay + (step number x TIL)).
10. SCLK has to transition L-H a setup time before the SLOAD H-L transition to ensure the valid data is properly latched. See timing diagram "Setup
and Hold Time: SCLK and SLOAD.”
11. This setup time is the minimum time that /EN must be asserted prior to the next transition of IN / /IN to prevent an output response greater than
±75 mV to that IN or /IN transition. See timing diagram Setup, Hold and Release Time: IN and /EN."
12. SCLK has to transition L-H a hold time after the SLOAD H-L transition to ensure that the valid data is properly latched before starting to load new
data. See timing diagram "Setup and Hold Time: SCLK and SLOAD.”
13. This hold time is the minimum time that /EN must remain asserted after a negative going transition of IN to prevent an output response greater than
+75mv to the IN transition. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
14. This release time is the minimum time that /EN must be de-asserted prior to the next IN / /IN transition to affect the propagation delay of IN to Q
less than 1ps. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
15. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs.
Tjitter_cc = Tn – Tn+1, where T is the time between rising edges of the output signal.
16. Total jitter definition: With an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-
peak jitter value.
17. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean.
Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.
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