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参数资料
| 型号： | SY89467UHYTR |
| 厂商： | MICREL INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封装： | LEAD FREE, TQFP-64 |
| 文件页数： | 12/15页 |
| 文件大小： | 558K |
| 代理商： | SY89467UHYTR |
Micrel, Inc.
SY89467U
April 2008
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics
(8)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50 to VCC-2V; Input tr/tf < 300ps; TA = –40°C to + 85°C, unless otherwise
stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOUT ≥ 200mV, VIN ≥ 200mV
1.5
2.0
GHz
fMAX
Maximum Operating Frequency
VOUT ≥ 200mV, VIN ≥ 100mV
1.0
1.5
GHz
Differential Propagation Delay
IN-to-Q
100mV < VIN ≤ 200mV, Note 9
600
850
1200
ps
IN-to-Q
200mV < VIN ≤ 800mV, Note 9
500
750
1100
ps
tpd
SEL-to-Q
VTH = VCC/2
350
600
850
ps
tS OE
Set-up Time
OE-to-IN
Note 10
300
ps
tH OE
Hold Time
IN-to-OE
Note 10
800
ps
Output-to-Output Skew
Note 11
15
35
ps
Input-to-Input Skew
Note 12
5
20
ps
tSKEW
Part-to-Part Skew
Note 13
300
ps
Clock
Random Jitter
Note 14
1
psRMS
Cycle-to-Cycle Jitter
Note 15
1
psRMS
Total Jitter
Note 16
10
psPP
tJITTER
Crosstalk-Induced Jitter
Note 17
0.7
psRMS
tr, tf
Output Rise/Fall Time (20% to 80%)
At full output swing.
110
170
250
ps
VIN > 200mV
45
55
%
Duty Cycle
100mV < VIN ≤ 200mV
45
55
%
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Propagation delay is measured with input tr, tf ≤ 300ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN.
See “Typical Operating Characteristics” for details.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
11. Output-to-Output skew is measured between two different outputs under identical transitions.
12. Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions.
13. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
14. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
15. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
16. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
17. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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