参数资料
型号: SY89482LMGTR
厂商: MICREL INC
元件分类: 时钟及定时
英文描述: LOW SKEW CLOCK DRIVER, QCC24
封装: 4 X 4 MM, LEAD FREE, MLF-24
文件页数: 2/16页
文件大小: 425K
代理商: SY89482LMGTR
Micrel, Inc.
SY89482L
April 2008
10
M9999-040808-A
hbwhelp@micrel.com or (408) 955-1690
Functional Description
Overall Function
The SY89482L is designed to accept a high-jitter
signal and provide ultra-low jitter CML-compatible
clock signal. Unlike normal buffers, SY89482L does
not transfer jitter across making it an ideal solution for
precision clock applications.
LC Voltage Control Oscillator (VCO)
The SY89482L uses an extremely low phase noise
VCO to prevent jitter at the output. At low frequencies,
the PLL produces more phase noise. To offset this
additional noise, the LC VCO provides an extremely
low phase noise signal that feeds to an output circuit.
Unlike many competitive VCOs, this VCO does not
require any external components.
External Loop Filter Considerations
The SY89482L features an external PLL loop filter
that allows users to tailor the PLLs behavior. It is
recommended that ceramic capacitors with NOP or
X7R dielectric be used because they have very low
effective series resistance. The SY89482L uses only a
single
external
filter
capacitor.
All
other
filter
components are on-chip. Internally, the filter has a
resistor in series with the external capacitor and a
much smaller capacitor in parallel with the series
combination of the internal resistor and external
capacitor. The selectable PLL bandwidths from 1kHz-
to-10kHz allows the user to select between different
loop filter values. The external capacitor must be
placed as close to the device pins as possible. While
laying out the board, keep any supply or signal traces
lines away from the capacitor. Loop filter capacitor
layout should include a quiet ground plane under the
loop filter capacitor and loop filter pins.
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power
supply filtering is very important. At a minimum,
VDDA, VDD, and all VDDO pins should be individually
connected using via to the power supply plane, and
separate bypass capacitors should be used for each
pin. To achieve optimal jitter performance, each power
supply pin should use separate instances of the circuit
shown in Power Supply Scheme, Figure 1, below.
Figure 1. Power Supply Scheme
Auto-Tuning
The SY89482L has an auto-tune circuit that enables
precision frequency calibration. Auto-tuning is initiated
on a LOW to HIGH transition on the RESET input.
Auto-tuning is also initiated during power-up. Auto-
tune requires a valid reference input.
Jitter Generation
Jitter generation is the amount of jitter generated by
the part at the output when there is no jitter present at
the input clock. While the VCO and PLL are sources
of jitter in a synthesizer, the different loop bandwidth
options
aid
in
reducing
jitter.
The
SY89482L
guarantees less than 2psRMS. See Jitter characteristics
subsection.
Phase Noise
The SY89482L has very low phase noise at 1kHz
offset from the center frequency. Phase noise is
measured at the output with a jitter-free signal injected
at the input. The loop bandwidth settings have a minor
impact on the phase noise values. For 10kHz loop
bandwidth, Micrel guarantees the phase noise less
than -80dBc/Hz. See Phase Noise curve.
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