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参数资料
| 型号： | SY89531LHZ |
| 厂商： | MICREL INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 622.08 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封装： | LEAD FREE, TQFP-64 |
| 文件页数： | 3/16页 |
| 文件大小： | 105K |
| 代理商： | SY89531LHZ |
11
Precision Edge
SY89531L
Micrel, Inc.
M9999-010808
hbwhelp@micrel.com or (408) 955-1690
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power supply
filtering is very important. At a minimum, V
CCA, VCC_Logic,
and all V
CCO pins should be individually connected using a
via to the power supply plane, and separate bypass
capacitors should be used for each pin. To achieve optimal
jitter performance, each power supply pin should use
separate instances of the circuit shown in Figure 4.
*For VCC_Analog,VCC_TTL, VCC1,
use ferrite bead = 200mA, 0.45
DC,
Murata P/N BLM21A1025
*For VCC_OUT use ferrite bead = 3A, 0.025
DC,
Murata, P/N BLM31P005
*Component size: 0805
1
F
22
F
0.01
F
Ferrite Bead*
“Power Supply”
side
“Device”
side
VCC
Pins
Figure 4. Power Supply Filtering
Output Logic Characteristics
See
“Output Termination Recommendations” for
illustrations. In cases where single-ended output is desired,
the designer should terminate the unused complimentary
output in the same manner as the normal output that is
begin used. Unused output pairs can be left floating. Unused
output banks can be switched off by tying the appropriate
FSEL pins to ground. Unused output pairs that are in a
bank that is disabled can be left floating, regardless of output
driver type.
LVPECL operation:
Typical voltage swing is 700mV
PP to 800mVPP into
50
.
Common mode voltage is V
CC–1.3V, typical.
100
termination across the output pair is NOT
recommended for LVPECL.
HSTL operation (Bank B):
Typical voltage swing is 250mV
PP to 450mVPP into
effective 50
.
Thermal Considerations
This part has an exposed die pad for enhanced heat
dissipation. We strongly recommend soldering the exposed
pad to a ground plane. Where this is not possible, we
recommend maintaining at least 500lfpm air flow.
For additional information on exposed-pad characteristics
and implementation details, see Amkor Technology’s write-
up at www.amkor.com.
FSEL_A2(1) (MSB)
FSEL_A1(1)
FSEL_A0(1) (LSB)
Output Divider
0
Output Disable Function, all outputs: Q = LOW, /Q = HIGH
0
1
VCO
÷ 2
0
1
0
VCO
÷ 4
0
1
VCO
÷ 6
1
0
VCO
÷ 8
1
0
1
VCO
÷ 10
1
0
VCO
÷ 12
1
VCO
÷ 18
POST-DIVIDE FREQUENCY SELECT TABLE (FSEL)
Note 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY89531LHZ TR | 功能描述:时钟合成器/抖动清除器 3.3V Programmable HSTL/LVPECL Synthesizer (Green) RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SY89531LHZTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND |
| SY89532L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89532L_08 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
| SY89532LHC | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:Precision Edge® 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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