参数资料
型号: SY89534LHZ
厂商: MICREL INC
元件分类: 时钟及定时
英文描述: 89534 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封装: LEAD FREE, TQFP-64
文件页数: 3/15页
文件大小: 106K
代理商: SY89534LHZ
11
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
Rate
FSEL
MSEL
REFCLK
Protocol
(MHz)
(Post Divider)
(Feedback Div.)
(MHz)
PSEL
FOUT
PCI
33
18
36
16.67
1
33
Fast Ethernet
100
6
40
15
1
100
1/8 FC
133
6
52
15.36
1
133
ESCON
200
4
50
16
1
200
SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS
NOTES:
1. 600MHz < (REFCLK
÷ PSEL × MSEL) < 1000MHz.
2. 14MHz
≤ (REFCLK ÷ PSEL) ≤ 20MHz.
3. Where two settings provide the user with the identical desired frequency, the setting with the higher PLL input reference frequency (and lower
feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept within
their respective ranges.
FOUT
REFCLK PSEL MSEL
FSEL
=
÷×
()
M3
M2
M1
M0
VCO Frequency(1)
0000
REFCLK
÷ PSEL × 34
0001
REFCLK
÷ PSEL × 36
0010
REFCLK
÷ PSEL × 38
0011
REFCLK
÷ PSEL × 40
0100
REFCLK
÷ PSEL × 42
0101
REFCLK
÷ PSEL × 44
0110
REFCLK
÷ PSEL × 48
0111
REFCLK
÷ PSEL × 50
1000
REFCLK
÷ PSEL × 52
1001
REFCLK
÷ PSEL × 54
1010
REFCLK
÷ PSEL × 56
1011
REFCLK
÷ PSEL × 60
1100
REFCLK
÷ PSEL × 62
1101
REFCLK
÷ PSEL × 66
1110
REFCLK
÷ PSEL × 30
1111
REFCLK
÷ PSEL × 32
FEEDBACK DIVIDE SELECT TABLE (MSEL)
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