参数资料
| 型号： | SY89535LHZ TR |
| 厂商： | Micrel Inc |
| 文件页数： | 15/15页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZR LVPECL/LVDS 64TQFP |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 类型： | 时钟/频率合成器 |
| PLL： | 带旁路 |
| 输入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:13 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-EP-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY89535LHZTR SY89535LHZTR-ND |
9
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
REFCLK Input Interface
The flexible REFCLK inputs are designed to accept any
differential to single-ended input signal within 300mV above
VCC and 300mV below ground.
Do not leave unused REFCLK inputs floating. Tie either the
true or complement inputs to ground, but not both. A logic zero
is achieved by connecting the complement input to ground
with the true input floating. For a TTL input, tie a 2.5k
resistor
between the complement input and ground. See “Input
Interface” section, Figures 4a through 4j.
Input Levels
LVDS, CML and HSTL differential signals may be connected
directly to the REFCLK inputs. Depending on the actual worst
case voltage seen, the minimum input voltage swing varies as
illustrated in the following table:
Input Voltage Range
Minimum Voltage Swing
0 to 2.4V
100mV
0 to VCC +0.3
200mV
R2
1.5k
R2
1.5k
R1
1.05k
R1
1.05k
GND
REFCLK
VCC
/REFCLK
Figure 3. Simplified Input Structure
Output Logic Characteristics
See
“Output Termination Recommendations” for
illustrations. In cases where single-ended output is desired,
the designer should terminate the unused complimentary
output in the same manner as the normal output that is being
used. Unused LVPECL output pairs can be left floating.
Unused LVDS output pairs should be terminated
w/100
across the pair.
LVPECL operation:
Typical voltage swing is 700mV
PP to 800mVPP into
50
.
Common mode voltage is V
CC–1.3V, typical.
100
termination across the output pair is NOT
recommended for LVPECL. See
“Output Termination”
section, Figures 3 to 5.
LVDS operation (SY89535L, Bank B)
Typical voltage swing is 250mV
PP to 450mVPP into
effective 50
.
Common mode voltage is 1.25V, typical.
100
termination across differential output pair is
fine.
Thermal Considerations
This part has an exposed die pad for enhanced heat
dissipation. We strongly recommend soldering the exposed
die pad to a ground plane. Where this is not possible, we
recommend maintaining at least 500lfpm air flow around the
part.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY89536L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89536L_05 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89536L_08 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89536LHC | 功能描述:IC SYNTHESIZR LVPECL/HSTL 64TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:Precision Edge® 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| SY89536LHCTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
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