参数资料
| 型号： | SY89535LHZ TR |
| 厂商： | Micrel Inc |
| 文件页数： | 9/15页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZR LVPECL/LVDS 64TQFP |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 类型： | 时钟/频率合成器 |
| PLL： | 带旁路 |
| 输入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:13 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-EP-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY89535LHZTR SY89535LHZTR-ND |
3
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTION
Pin Number
Pin Name
Functional Description
4
VCO_SEL
LVTTL/CMOS Compatible Input: Selects between internal or external VCO. When
tied LOW (GND) internal VCO is selected. For external VCO, leave floating (default
condition is logic HIGH). Internal 25k
pull-up.
5, 6
PSEL(1:0)
LVTTL/CMOS Compatible Input: Controls input frequency pre divider. Internal 25k
pull-up. Default is logic HIGH. See
“Pre-Divide Frequency Select” table.
7
LOOP REF
Analog Input/Output: Provides the reference voltage for PLL loop filter.
8
LOOP FILTER
Analog Input/Output: Provides the loop filter for PLL. See
“External Loop Filter
Considerations” for loop filter values.
13,14,15,16
M (3:0)
LVTTL/CMOS Compatible Input: Used to change the PLL (Phase-Lock Loop)
feedback divider. Internal 25k
pull-up. (M0 = LSB). Default is logic HIGH.
See
“Feedback Divide Select” table.
22, 23, 24
FSEL_C (2:0)
LVTTL/CMOS Compatible Input: Bank C post divide select. Internal 25k
pull-up.
Default is logic HIGH. See
“Post-Divide Frequency Select” table.
26, 27, 28
FSEL_B (2:0)
LVTTL/CMOS Compatible Input: Bank B post divide select. Internal 25k
pull-up.
Default is logic HIGH. See
“Post-Divide Frequency Select” table.
56, 57, 58
FSEL_A (2:0)
LVTTL/CMOS Compatible Input: Bank A post divide select. Internal 25k
pull-up.
Default is logic HIGH. See
“Post-Divide Frequency Select.” FSEL_A0 = LSB.
59
OUT_SYNC
Banks A,B,C output synchronous control: (LVTTL/CMOS compatible).
Internal 25k
pull-up. After any bank has been programmed, toggle with a
HIGH-LOW-HIGH pulse to resynchronize all output banks.
Configuration
Pin Number
Pin Name
Functional Description
60, 61
V
CC_Logic
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
62
V
CCA
Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
55
V
CCOA
Power for Output Drivers: Connect all V
CCO pins to 3.3V supply. VCCO pins are not
30, 31, 50
V
CCOB
connected internally on the die.
21
V
CCOC
4, 9, 25, 63, 29
GND
Ground. All GND pins must be tied together on the PCB. Exposed pad must be
(exposed pad)
soldered to a ground plane.
Power
Pin Number
Pin Name
Functional Description
1, 2, 3
NC
No Connect: Leave floating.
10, 11
REFCLK, /REFCLK
Reference Input: This flexible input accepts any input TTL/CMOS, LVPECL, LVDS,
HSTL, SSTL. See
“Input Interface” section.
12
VBB_REF
Reference Output Voltage. Used for single-ended input. Maximum sink/source
current = 0.5mA.
51, 52, 53, 54
QA1 to QA0
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A
(0:2). Terminate outputs with 50
to V
CC –2V. See “Output Termination
Recommendations” section for termination detail.
32–49
QB8 to QB0
Bank B Output Drivers: SY89534: 100k LVPECL output drivers.
SY89535: Differential LVDS outputs. See
“Output Termination Recommendations”
section for termination detail. Output frequency is controlled by FSEL_B (0:2).
17, 18, 19, 20
QC1 to QC0
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by
FSEL_C (0:2). Terminate outputs with 50
to V
CC–2V. See “Output Termination
Recommendations” section.
64
NC
No Connect: Leave floating.
Input/Output
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| SY89536LHC | 功能描述:IC SYNTHESIZR LVPECL/HSTL 64TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:Precision Edge® 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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