参数资料
| 型号： | SY89809LTH TR |
| 厂商： | Micrel Inc |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:9 32-TQFP |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:9 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HSTL，LVPECL |
| 输出： | HSTL |
| 频率 - 最大： | 500MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY89809LTHTR SY89809LTHTR-ND |
Micrel, Inc.
SY89809L
December 2009
5
M9999-121409-D
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
(4)
TA = 0°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
tPD
Propagation Delay
(5)
825
1050
1275
ps
fMAX
Maximum Operating Frequency
(6)
500
MHz
tSKEW
Within-Device Skew
(7)
50
ps
tSKPP
Part-to-Part Skew
(8)
200
ps
tJITTER
Phase Noise(RMS)
12kHz-20MHz @ 500MHz
See Figure 3
0.241
1
ps
VPP
Minimum Input Swing
(9)
LVPECL_CLK
600
mV
VCMR
Common Mode Range
(10)
LVPECL_CLK
–1.5
–0.4
V
tS
OE Set-Up Time
(11)
1.0
ns
tH
OE Hold Time
0.5
ns
tr, tf
Output Rise/Fall Time
(20% to 80%)
300
650
ps
Notes:
4.
Outputs loaded with 50 to ground. Airflow ≥ 300lfpm.
5.
Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
6.
Output swing greater than 450mV.
7.
The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
8.
The part-to-part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
9.
The VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
10. VCMR is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The numbers in
the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min).
11. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next
clock cycle.
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