参数资料
型号: SY89823LHY
厂商: Micrel Inc
文件页数: 4/8页
文件大小: 0K
描述: IC CLK BUF MUX TRNSL 2:22 64TQFP
标准包装: 160
系列: Precision Edge®
类型: 扇出缓冲器(分配),多路复用器,变换器
电路数: 1
比率 - 输入:输出: 2:22
差分 - 输入:输出: 是/是
输入: HSTL,LVPECL
输出: HSTL
频率 - 最大: 500MHz
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-TQFP 裸露焊盘
供应商设备封装: 64-EP-TQFP
包装: 托盘
产品目录页面: 1083 (CN2011-ZH PDF)
其它名称: 576-2090
SY89823LHY-ND
4
Precision Edge
SY89823L
Micrel, Inc.
M9999-091908
hbwhelp@micrel.com or (408) 955-1690
DC ELECTRICAL CHARACTERISTICS(5)
LVCMOS/LVTTL V
CCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
——
V
IL
Input LOW Voltage
——
0.8
V
I
IH
Input HIGH Current
+20
—–250
A
I
IL
Input LOW Current
——
–600
A
VCCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; All outputs loaded with 50 to GND; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
VOUT ≥ 450mV
500
——
MHz
tpd
Propagation Delay
CLK-to-Q
Note 7
0.8
1.3
ns
SEL-to-Q
Note 7
0.8
1.2
1.7
ns
tSKEW
Within-Device Skew
Note 8
——
50
ps
tSKPP
Part-to-Part Skew
Note 9
——
200
ps
Vpp
Minimum Input Swing
Note 10
600
——
mV
LVPECL_CLK
VCMR
Common Mode Range
Note 11
–1.5
—–0.4
V
LVPECL_CLK
tS
OE Set-Up Time
Note 12
1.0
——
ns
tH
OE Hold Time
0.5
——
ns
tr, tf
Output Rise/Fall Time (20% – 80%)
300
700
ps
tJITTER
Cycle-to-Cycle Jitter
Note 13
1psRMS
Notes:
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. High-frequency AC-parameters are guaranteed by design and characterization.
7. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
8. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the
same voltage and temperature.
9. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
10. The VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
11. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The
numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or
equal to VPP(min). The lower end of the CMR range varies 1:1 with VCCI. The VCMR(min) will be fixed at 3.3V – |VCMR(min)|.
12. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the
next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock.
13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the
output signal.
AC ELECTRICAL CHARACTERISTICS(6)
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