参数资料
| 型号： | SY89871UMI TR |
| 厂商： | Micrel Inc |
| 文件页数： | 1/11页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFF DIVIDER 1:3 16-MLF |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 类型： | 扇出缓冲器（分配），除法器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，HSTL，LVDS，LVPECL |
| 输出： | LVPECL |
| 频率 - 最大： | 2.5GHz |
| 电源电压： | 2.375 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘，16-MLF? |
| 供应商设备封装： | 16-MLF?（3x3） |
| 包装： | 带卷 (TR) |
| 其它名称： | SY89871UMITR SY89871UMITR-ND |
SY89871U
2.5GHz Any Diff. In-To-LVPECL
Programmable Clock Divider/Fanout Buffer
w/ Internal Termination
Precision Edge is a registered trademark of Micrel, Inc
Micre
l Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
Oct. 1, 2013
M9999-010512-F
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8, and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock
components.
The
differential
input
buffer
has
a
unique
internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output banks.
Bank A (QA) is a frequency-matched copy of the input.
Bank B (QB0, QB1) is a divided down output of the input
frequency. Bank A and Bank B maintain a matched delay
independent of the divider setting.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Typical Performance
Precision Edge
Features
Two matched-delay outputs:
- Bank A: undivided pass-through (QA)
- Bank B: programmable divide by 2, 4, 8, 16 (QB0,
QB1)
Matched delay: all outputs have matched delay,
independent of divider setting
Guaranteed AC performance:
- >2.5GHz fMAX
- <250ps tr/tf
- <670ps tpd (matched delay)
- <15ps within-device skew
Low jitter design
- 231fs RMS phase jitter (Typ)
Power supply 3.3V or 2.5V
Unique patent-pending input termination and VT pin for
DC- and AC- coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
Applications
OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards
相关PDF资料 |
PDF描述 |
|---|---|
| SY89872UMI TR | IC CLK BUFF DVDR 1:3 2GHZ 16-MLF |
| SY89873LMI TR | IC CLK BUFF DVDR 1:3 2GHZ 16-MLF |
| SY89874UMI TR | IC CLOCK BUFF DIVIDER 1:2 16-MLF |
| SY89875UMI TR | IC CLK BUFF DVDR 1:2 2GHZ 16-MLF |
| SY89876LMI TR | IC CLK BUFF DVDR 1:2 2GHZ 16-MLF |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SY89872U | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION |
| SY89872U_0708 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS |
| SY89872UMG | 功能描述:时钟驱动器及分配 2.5V LVDS Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| SY89872UMG TR | 功能描述:时钟驱动器及分配 2.5V LVDS Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| SY89872UMGTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION |
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