参数资料
| 型号： | SY89871UMI TR |
| 厂商： | Micrel Inc |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFF DIVIDER 1:3 16-MLF |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 类型： | 扇出缓冲器（分配），除法器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，HSTL，LVDS，LVPECL |
| 输出： | LVPECL |
| 频率 - 最大： | 2.5GHz |
| 电源电压： | 2.375 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘，16-MLF? |
| 供应商设备封装： | 16-MLF?（3x3） |
| 包装： | 带卷 (TR) |
| 其它名称： | SY89871UMITR SY89871UMITR-ND |
7
SY88773V
Micrel, Inc.
M9999-110905
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88773V low-power, limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40
°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mVpp can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88773V generates
an LOS output, providing feedback to /EN for output stability.
LOSLVL sets the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
The SY88773V input is designed for VREF as its nominal
DC bias point. If AC-coupling to the SY88773V, REF can
be used as the DC bias point by externally connecting the
inputs through appropriate termination resistors to REF. If
DC-coupling to the SY88773V, ensure the upstream device’s
output swing meets the SY88773V’s common mode range.
Figure 2 shows a simplified schematic of the input structure.
The high-sensitivity of the input amplifier detects and
amplifies signals as small as 10mVpp. The input amplifier
allows input signals as large as 1800mVpp. Input signals
are linearly amplified with a typically 38dB differential voltage
gain. Since it is a limiting amplifier, the SY88773V outputs
typically 800mVpp voltage-limited waveforms for input signals
that are greater than 10mVpp. Applications requiring the
SY88773V to operate with high-gain should have the
upstream TIA placed as close as possible to the SY88773V’s
input pins to ensure the device’s best performance.
Output Buffer
The SY88773V’s CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to VCC or
equivalent for each output pin provides appropriate output
buffer termination. Figure 3 shows a simplified schematic of
the output structure and includes an appropriate termination
method. Of course, driving a downstream device with a
CML input that is internally terminated with 50
to VCC
eliminates the need for external termination. As noted in
the previous section, the amplifier outputs, typically 800mVpp,
waveforms across 25
total loads. The output buffer, thus,
switches typically 16mA tail-current. Figure 4 shows the
power supply current measurement which excludes the
16mA tail-current.
Loss-of-Signal
The SY88773V incorporates a chatter-free, LOS open-
collector TTL output with internal 4.75k
pull-up resistor as
shown in Figure 5. LOS is used to determine that the input
amplitude is too small to be considered a valid input. LOS
asserts high if the input amplitude falls below the threshold
set by LOSLVL and de-asserts low otherwise. LOS can be
fed back to the enable (/EN) input to maintain output stability
under a loss-of-signal condition. /EN de-asserts low the
true output signal without removing the input signals.
Typically, 4.6dB LOS hysteresis is provided to prevent
chattering.
Loss-of-Signal Level Set
A programmable, loss-of-signal level set pin sets the
threshold of the input amplitude detection. Connecting an
external resistor between VCC and LOSLVL sets the voltage
at LOSLVL. This voltage ranges from V
CC to VREF. The
external resistor creates a voltage divider between VCC
and REF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The relationship between VLOSLVL and RLOSLVL is given by:
VV
–
R
R+
LOSLVL
CC
LOSLVL
=
13
28
.
where voltages are in volts and resistances are in k
.
The smaller the external resistor, which implies a smaller
voltage difference from LOSLVL to VCC, the lower the LOS
sensitivity. Hence, larger input amplitude is required to de-
assert LOS. The “Typical Operating Characteristics” section
contains graphs showing the relationship between the input
amplitude detection sensitivity and VLOSLVL or RLOSLVL.
Hysteresis
The SY88773V provides typically 4.6dB LOS electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and,
hence, the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88773V provides typically 2.3dB
LOS optical hysteresis. As the SY88773V is an electrical
device, this datasheet refers to hysteresis in electrical terms.
With 4.6dB LOS hysteresis, a voltage factor of 1.7 is required
to de-assert LOS.
Hysteresis and Sensitivity Improvement
If increased LOS sensitivity and hysteresis are required,
an application note entitled “Notes on Sensitivity and
Hysteresis in Micrel Post Amplifiers” is available at http://
www.micrel.com/product-info/app_hints+notes.shtml.
相关PDF资料 |
PDF描述 |
|---|---|
| SY89872UMI TR | IC CLK BUFF DVDR 1:3 2GHZ 16-MLF |
| SY89873LMI TR | IC CLK BUFF DVDR 1:3 2GHZ 16-MLF |
| SY89874UMI TR | IC CLOCK BUFF DIVIDER 1:2 16-MLF |
| SY89875UMI TR | IC CLK BUFF DVDR 1:2 2GHZ 16-MLF |
| SY89876LMI TR | IC CLK BUFF DVDR 1:2 2GHZ 16-MLF |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SY89872U | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION |
| SY89872U_0708 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS |
| SY89872UMG | 功能描述:时钟驱动器及分配 2.5V LVDS Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| SY89872UMG TR | 功能描述:时钟驱动器及分配 2.5V LVDS Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| SY89872UMGTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION |
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