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参数资料
| 型号： | SYS32128LKL-017 |
| 元件分类： | SRAM |
| 英文描述： | 128K X 32 MULTI DEVICE SRAM MODULE, 17 ns, PSMA64 |
| 封装： | PLASTIC, SIMM-64 |
| 文件页数： | 6/7页 |
| 文件大小： | 167K |
| 代理商： | SYS32128LKL-017 |
ISSUE 1.3 January 1999
SYS32128ZK/LK - 010/012/015/017
6
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS1~4 and a low WE.
(2) All write cycle timing is referenced from the last valid address to the first transition address.
(3) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output
voltage levels. These parameters are sampled and not 100% tested.
(4) At any given temperature and voltage condition, tWHZ (max) is less than tOW (min) both for a given
module and from module to module.
(5) Module is continuously selected with CS1~4 = VIL.
(6) CS1~4 or WE must be high during address transition.
(7) WE is High for Read Cycle.
(8) All read cycle timing is referenced from the last valid address to the first transition address.
(9) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given
module
and from module to module.
(10) Address is valid prior to or coincident with CS1~4 transition low.
Write Cycle No.2 Timing Waveform (1-10)
CW
WR
WC
AS
DW
DH
OH
OW
WHZ
AW
WP
Don't
t
Address
CS1~4
WE
Dout
Din
t
Care
High-Z
Data Retention Waveform
tR
t
CDR
4.5V
DATA RETENTION MODE
Vcc
V DR
VIH
V DR
VIL
CS1~4
Don't
care
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| SYS32128LKLI-010 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 SRAM Module |
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