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参数资料
| 型号： | T4260ILS |
| 厂商： | ATMEL CORP |
| 元件分类： | 调谐器 |
| 英文描述： | AUDIO TUNER, PDSO44 |
| 封装： | SSO-44 |
| 文件页数： | 30/30页 |
| 文件大小： | 299K |
| 代理商： | T4260ILS |
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9
T4260
4528I–AUDR–08/04
3-wire Bus Description
The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus
protocol consists of separate commands. A defined number of bits is transmitted
sequentially during each command.
One command is used to program all bits of one register. The different registers avail-
able (see chapter “3-wire Bus Data Transfer” on page 11) are addressed by the length
of the command (number of transmitted bits) and by two address bits that are unique to
each register of a given length. 8-bit registers are programmed by 8-bit commands,
16-bit registers are programmed by 16-bit commands and 24-bit registers are pro-
grammed by 24-bit commands.
Each bus command starts with a falling edge on the enable line (EN) and ends with a
rising edge on EN. EN has to be kept LOW during the bus command.
The sequence of transmitted bits during one command starts with the MSB of the first
byte and ends with the LSB of the last byte of the register addressed. To transmit one bit
(0/1), DATA has to be set to the appropriate value (LOW/HIGH) and a LOW-to-HIGH
transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is
evaluated at the rising edges of CLK. The number of LOW-to-HIGH transitions on CLK
during the LOW period of EN is used to determine the length of the command.
Figure 3. 3-wire Pulse Diagram
8-bit command
EN
CLK
DATA
MSB
LSB
BYTE 1
24-bit command
16-bit command
DATA
CLK
MSB
LSB
BYTE 1
BYTE 2
EN
CLK
DATA
MSB
LSB
BYTE 3
BYTE 2
LSB
MSB
BYTE 1
EN
e.g. R-divider
27
X
R-Divider
Addr.
VCO-Divider
0
1
Fract.
PDAM
PDFM
26
25
24
23
22
21
20
213
212
211
210
29
28
23
22
21
20
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