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| 型号： | T436416D-7S |
| 厂商： | TM Technology, Inc. |
| 英文描述： | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 4米× 16 SDRAM的100万x 16Bit的X 4Banks同步DRAM |
| 文件页数： | 6/73页 |
| 文件大小： | 734K |
| 代理商： | T436416D-7S |
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TE
CH
tm
Commands
T436416D
TM Technology Inc. reserves the right
P. 6
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0,1 signals. By latching the row
address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write
operation in the same bank can occur after a time delay of t
RCD
(min.) from the time of bank activation. A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure). The minimum time interval between successive
BankActivate commands to the same bank is defined by t
RC
(min.). The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of the four banks. t
RRD
(min.) specifies the minimum time required between activating different banks.
After this command is used, the Write command and the Block Write command perform the no mask write
operation.
CLK
ADDRESS
T0
T 1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
..............
COMMAND
..............
..............
NOP
NOP
NOP
NOP
RAS# - CAS# delay (
t
RCD
)
RAS# - RAS# delay time (
t
RRD
)
RAS# Cycle time (
t
RC
)
Bank A
Row Addr.
Bank A
Col Addr.
Bank B
Row Addr.
Bank A
Row Addr.
Bank A
Activate
R/W A with
AutoPrecharge
Bank B
Activate
Bank A
Activate
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle
(Burst Length = n, CAS# Latency = 3)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
The BankPrecharge command precharges the bank designated by BA signal. The precharged bank is
switched from the active state to the idle state. This command can be asserted anytime after t
RAS
(min.) is
satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is
specified by t
RAS
(max.). Therefore, the precharge function must be performed in any active bank within
t
RAS
(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated
again.
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9 and A11 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are
not in the active state. All banks are then switched to the idle state.
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before the Read command is issued. During read
bursts, the valid data-out element from the starting column address will be available following the CAS#
latency after the issue of the Read command. Each subsequent data-out element will be valid by the next
positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst
unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the
mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the
page it will wrap to column 0 and continue).
相关PDF资料 |
PDF描述 |
|---|---|
| T436416D-7SG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436432B-5S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-5SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-6S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-6SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| T436416D-7SG | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436432B | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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