参数资料
型号: T436416D
厂商: TM Technology, Inc.
英文描述: 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
中文描述: 4米× 16 SDRAM的100万x 16Bit的X 4Banks同步DRAM
文件页数: 10/73页
文件大小: 734K
代理商: T436416D
TE
CH
tm
T436416D
TM Technology Inc. reserves the right
P. 10
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don't care
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge
function should be issued
m
cycles after the clock edge in which the last data-in element is registered, where
m
equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM signals must be used to mask input
data, starting with the clock edge following the last data-in element and ending with the clock edge on which
the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
CLK
T0
T 1
T2
T3
T4
T5
T6
WRITE
COMMAND
BANK (S)
ROW
NOP
NOP
Precharge
NOP
NOP
Activate
BANK
COL n
DIN
n
DIN
n + 1
DQM
ADDRESS
DQ
tWR
tRP
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
7
Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A7
= Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the write
operation. Once this command is given, any subsequent command can not occur within a time delay of
{
(burst
length -1) + t
WR
+ t
RP
(min.)
}
. At full-page burst, only the write operation is performed in this command and the
auto precharge function is ignored.
相关PDF资料
PDF描述
T436416D-5C 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-5CG 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-5S 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-5SG 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-6C 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
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T436416D-5CG 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-5S 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-5SG 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
T436416D-6C 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM