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参数资料
| 型号： | T436432B |
| 厂商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200万× 32内存为512k × 32 x 4Banks同步DRAM |
| 文件页数： | 11/72页 |
| 文件大小： | 731K |
| 代理商： | T436432B |
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TE
CH
tm
7
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the write
operation. Once this command is given, any subsequent command can not occur within a time delay of
{
(burst
length -1) + t
WR
+ t
RP
(min.)
}
. At full-page burst, only the write operation is performed in this command and the
auto precharge function is ignored.
T436432B
TM Technology Inc. reserves the right
P. 11
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
DIN A1
DIN A0
DIN A1
*
*
*
t
DAL
=
t
WR
+
t
RP
Begin AutoPrecharge
Bank can be reactivated at completion of
t
DAL
Bank A
AutoPrecharge
t
DAL
t
DAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)
8
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode
register to make SDRAM useful for a variety of different applications. The default values of the Mode Register
after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of
pins BS0,1 and A10~A0 in the same cycle is the data written to the mode register. One clock cycle is required
to complete the write in the mode register (refer to the following figure). The contents of the mode register can
be changed using the same command and the clock cycle requirements during operation as long as all banks are
in the idle state.
相关PDF资料 |
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| T436432B-10S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| T436432B-10S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55SG | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-5S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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