- 您现在的位置：买卖IC网 > PDF目录361344 > T436432B (TM Technology, Inc.) 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM PDF资料下载
参数资料
| 型号： | T436432B |
| 厂商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200万× 32内存为512k × 32 x 4Banks同步DRAM |
| 文件页数： | 9/72页 |
| 文件大小： | 731K |
| 代理商： | T436432B |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
TE
CH
tm
T436432B
TM Technology Inc. reserves the right
P. 9
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
COMMAND
CAS# latency=2
tCK2, DQ's
T0
T 1
T2
T3
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP
NOP
Activate
NOP
NOP
Precharge
CAS# latency=3
tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
ADDRESS
t
RP
Bank,
Col A
Bank(s)
Bank,
Row
Read to Precharge (CAS# Latency = 2, 3)
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command cannot occur within a time delay of
{
t
RP
(min.)
+ burst length
}
. At full-page burst, only the read operation is performed in this command and the auto precharge
function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN A3
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Extra data s masked.
don't care
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
相关PDF资料 |
PDF描述 |
|---|---|
| T436432B-10S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T494D156M025AS | SOLID TANTALUM CHIP CAPACITORS<br>(T494 SERIES - Low ESR, Industrial Grade) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| T436432B-10S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55SG | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-5S | 制造商:TMT 制造商全称:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
发布紧急采购，3分钟左右您将得到回复。