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参数资料
| 型号： | T6B70BFNG |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封装： | 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-16 |
| 文件页数： | 16/21页 |
| 文件大小： | 367K |
| 代理商： | T6B70BFNG |
T6B70BFNG
2008-05-15
4
2. Amplifier input circuit and signal detection/non-detection circuit (reception block)
The modulation signal input block is equipped with high and a low comparator to detect only when the
external sine wave signal’s amplitude is above the defined threshold. In this way, signals with amplitudes
lower than the specified threshold (e.g., noise signals) are prevented from being mistakenly detected as sine
waves.
The detection frequency range (frequency window) is determined by the divider ratio 1/17 to 1/15 of Fosc.
Detection/non-detection confirmation conditions are such that when the signals within the specified
frequency range are detected (or not detected) in succession, the signals are controlled. It takes about 9 to 15
waves (based on Fosc 1/16 frequency) to make detection/non-detection confirmation in this manner.
VH
VL
Input
sensitivity
VPP
Reception detected
AMP IN input sine waveform
Reception non-detected
VH
VL
VBIAS
Held at high
VBIAS
< VL
VBIAS
> VH
VH
> VBIAS > VL VH > VBIAS > VL
AMPOUT output timing (/RESET
= L)
AMPOUT
Held at low
AMPOUT Truth Table
VA
VB
AMPOUT
VBIAS
> VH
L
H
L
VH
> VBIAS > VL
H
Hold
VBIAS
< VL
H
L
H
7
AMPIN pin
R1
R2
R3
R4
VSS
Reference
voltage
VDD
VH
+
VBIAS
Reference
voltage
VL
High comparator
VA
Low comparator
VB
R
S
Q
+
Cycle
measurement
counter
Detection
/non-detection
judgment
circuit
9
/DOUT pin
6
AMPOUT pin
VDD
VSS
APU
RESET
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