参数资料
型号: T6B70BFNG
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封装: 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-16
文件页数: 17/21页
文件大小: 367K
代理商: T6B70BFNG
T6B70BFNG
2008-05-15
5
3. Transmission block function and timing
When the modulation control input (/SCTL) is in High-level, the pseudo sine wave output is held at 0° phase
of the pseudo sine wave. When the modulation control input changes from High-level to Low-level, the
pseudo sine wave output (SOUT
+) initially outputs from -90° (SOUT outputs from +90°).
The time required to turn ON in this case is as follows:
td (ON)
< 500 ns
When modulation control input changes from Low-level to High-level, the phase is forcibly held at 0° (the
pseudo sine wave output is stopped), regardless of the phase of the pseudo sine wave output. The time
required to turn OFF in this case is as follows:
td (OFF)
< 1 μs
4. Reception block function and timing
Once it is okay to receive the amplifier input signal, the time it takes for the /DOUT pin to changes from
High to Low (T (DET)) is about 9 to 15 waves (based on Fosc 1/16 frequency). This condition is only valid
when the cyclic input signal within the range specified by the frequency window is detected (or not detected)
in continuation.
Note 1: You are free to use any kind of communication protocol you wish, however be sure to configure a time of
carrier wave
× 15 waves or more for both when there are and aren’t signals.
/SCTL
td (ON)
~~
td (OFF)
SOUT
+ pseudo sine wave output
(SOUT
is the opposite polarity)
Amplifier input
T (DET)
~~
T (DET)
/DOUT
~~
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