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参数资料
型号： T89C51CC02UA-TISIM
厂商： Atmel
文件页数： 76/159页
文件大小： 0K
描述： IC 8051 MCU FLASH 16K 28SOIC
标准包装： 27
系列： AT89C CAN
核心处理器： 8051
芯体尺寸： 8-位
速度： 40MHz
连通性： CAN，UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 20
程序存储器容量： 16KB（16K x 8）
程序存储器类型： 闪存
EEPROM 大小： 2K x 8
RAM 容量： 512 x 8
电压 - 电源 (Vcc/Vdd)： 3 V ~ 5.5 V
数据转换器： A/D 8x10b
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 28-SOIC（0.295"，7.50mm 宽）
包装： 管件
配用： AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名称： T89C51CC02UATISIM
23
AT/T89C51CC02
4126L–CAN–01/08
Exiting Power-down Mode
Note:
If
V
DD was reduced during the Power-down mode, do not exit Power-down mode until
V
DD is restored to the normal operating level.
There are two ways to exit the Power-down mode:
1.
Generate an enabled external interrupt.
–
The A/T89C51CC02 provides capability to exit from Power-down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (See Figure 8). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-down mode.
Notes:
1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,
the duration of the interrupt must be long enough to allow the oscillator to stabilize.
The execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.
Figure 8. Power-down Exit Waveform Using INT1:0#
2.
Generate a reset.
–
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the A/T89C51CC02 and
vectors the CPU to address 0000h.
Notes:
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
INT1:0#
OSC
Power-down phase
Oscillator restart phase
Active phase
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