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参数资料
| 型号： | TAS3001CPW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28 |
| 封装： | GREEN, PLASTIC, TSSOP-28 |
| 文件页数： | 6/55页 |
| 文件大小： | 432K |
| 代理商： | TAS3001CPW |
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21
2 Audio Data Formats
2.1
Serial Audio Interface
The TAS3001 operates in digital audio slave mode only. The TAS3001 supports three serial audio data formats: I2S,
left-justified, and right-justified. Data word lengths of 16, 18, and 20 bits are supported.
Data is input into SDIN1 and SDIN2 under the influence of the master clock (MCLK), left/right clock (LRCLK), and
shift clock (SCLK) inputs.
Data is output on the SDOUT pin under the influence of the master clock (MCLK) input plus the left/right clock
(LRCLKOUT) and shift clock (SCLKOUT) outputs. LRCLKOUT and SCLKOUT are generated from the MCLK input
(usually at 256
× fs). Typically these are routed on the PCB to LRCLK (as the input fs sample clock) and SCLK (as
the input 64
× fs bit clock).
The TAS3001 device is compatible with 10 different serial interfaces. Available interface options are I2S,
right-justified, and left-justified. Table 21 and Table 22 indicate how the 10 options are selected using the I2C bus
and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, or 20 bits operate
with SCLK at 64
× fs. The 16-bit mode, left-justified, can operate at 32 × fs or 64 × fs.
Table 21. Serial Interface Input Options
MODE
MCR BIT 6
SC
MCR BITS 32
F(1,0)
MCR BITS 10
W(1,0)
SERIAL INTERFACE
SDIN1, SDIN2
0
00
16-bit, left-justified, 32
× fs
1
00
16-bit, left-justified, 64
× fs
2
1
01
00
16-bit, right-justified, 64
× fs
3
1
10
00
16-bit, I2S, 64
× fs
4
1
00
01
18-bit, left-justified, 64
× fs
5
1
01
18-bit, right-justified, 64
× fs
6
1
10
01
18-bit, I2S, 64
× fs
7
1
00
10
20-bit, left-justified, 64
× fs
8
1
01
10
20-bit, right-justified, 64
× fs
9
1
10
20-bit, I2S, 64
× fs
Table 22. Serial Interface Output Options
MODE
MCR BIT 6
SC
MCR BITS 54
E(1,0)
MCR BITS 10
W(1,0)
SERIAL INTERFACE
SDOUT
0
00
16-bit, left-justified, 32
× fs
1
00
16-bit, left-justified, 64
× fs
2
1
01
00
16-bit, right-justified, 64
× fs
3
1
10
00
16-bit, I2S, 64
× fs
4
1
00
01
18-bit, left-justified, 64
× fs
5
1
01
18-bit, right-justified, 64
× fs
6
1
10
01
18-bit, I2S, 64
× fs
7
1
00
10
20-bit, left-justified, 64
× fs
8
1
01
10
20-bit, right-justified, 64
× fs
9
1
10
20-bit, I2S, 64
× fs
Figure 21 through Figure 24 illustrate the relationship between the SCLK, LRCLK, and the serial data input and
output protocol options.
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相关代理商/技术参数 |
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| TAS3001CPWG4 | 功能描述:音频 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS3001CPWR | 功能描述:音频 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS3001CPWRG4 | 功能描述:音频 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS3001EVM | 制造商:Texas Instruments 功能描述:TAS3001 EVALUATION BOARD - Bulk |
| TAS3001IN WAF | 制造商:Texas Instruments 功能描述: |
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