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参数资料
| 型号： | TAS3202PAGR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 18/66页 |
| 文件大小： | 817K |
| 代理商： | TAS3202PAGR |
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D7
D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
LastDataByte
A6
A5
A1
A0 R/W ACK A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
FirstDataByte
A4
A3
A6
OtherDataBytes
ACK
Acknowledge
D0
D7
D0
T0036-02
A6
A0
ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
T0036-04
www.ti.com
SLES208B – JUNE 2009 – REVISED MARCH 2011
Sequential I2C Transactions
The TAS3202 also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS3202. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written to. As was true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data
is discarded.
Sequential read transactions do not have restrictions on outputting only complete subaddress data sets.
If the master does not issue enough data-received acknowledges to receive all the data for a given
subaddress, the master device simply does not receive all the data.
If the master device issues more data-received acknowledges than required to receive the data for a given
subaddress, the master device simply receives complete or partial sets of data, depending on how many
data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both
sequential and random, can impose I2C clock stretching..
6.3.1
Multiple-Byte Write
Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-4. After receiving
each data byte, the TAS3202 responds with an acknowledge bit.
Figure 6-4. Multiple-Byte Write Transfer
6.3.2
Multiple-Byte Read
Multiple data bytes are transmitted by the TAS3202 to the master device as shown in Figure 6-5. Except
for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 6-5. Multiple-Byte Read Transfer
6.4
I
2C Master-Mode Device Initialization
I2C master-mode operation is enabled following a reset or power-on reset. Master-mode I2C transactions
do not start until the I2C bus is idle.
Copyright 2009–2011, Texas Instruments Incorporated
Microprocessor Controller
25
Product Folder Link(s): TAS3202
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