I C Sub Address x 00
2
S Slave Addr
Sub Addr
Ack
IM
Res
OM
Res
ON
OW
Res
IW
Res
CMS
31
25
24
23
21
18
16
15
13
11
9
7
5
3
1
0
I C Sub Address x 01
2
S Slave Addr
Sub Addr
Ack
N
Ack
Res
Ack
Ack Res
Ack
M
Res
31
23
15
7
6
2
0
CLOCK MASTER SELECT
CMS
0
Clock slave mode
1
Master mode
SAP OUTPUT NORMALIZATION
ON
0
Normalization disable
1
Normalization enable
OUTPUT SAP WORD SIZE
16-bit
20-bit
24-bit
OW[1]
0
1
OW[0]
0
1
0
1
Reserved
INPUT SAP WORD SIZE
16-bit
20-bit
24-bit
IW[1]
0
1
IW[0]
0
1
0
1
Reserved
INPUT SAP MODE
Left-justified
Right-justified
I S
2
IM[1]
0
1
IM[0]
0
1
0
1
Reserved
OUTPUT SAP MODE
Left-justified
Right-justified
I S
2
OM[1]
0
1
OM[0]
0
1
0
1
Reserved
Clock Master Operation
Clock Slave Operation
www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008
Figure 4. Clocking System I2C Mapping
When configured as the device clock master, an external crystal is used as a reference to an internal oscillator.
In this mode of operation, all internal clocks are generated by the oscillator.
LRCLKOUT is fixed at 48 kHz (Fs)
SCLKOUT is fixed at 64 Fs
MCLKOUT is fixed 256 Fs
When configured as the device clock Slave, the DAP, MCU, and I2C interface are derived from the external
crystal, however the digital audio clocks are supplied externally.
Internal analog clocks for the analog to digital converter (ADC) and digital to analog converter (DAC) are derived
from the MCLKIN input. As a result, analog performance will depend on the quality of MCLKIN.
Degradation in analog performance is to be expected depending on the quality of MCLKIN.
The TAS3218 device does not include any internal clock error or click/pop detection/management. The muting of
the outputs at updating of sample rate dependent coefficients must be initiated by the host system controller.
Copyright 2008, Texas Instruments Incorporated
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