参数资料
型号: TAS5026APAGR
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 9/64页
文件大小: 936K
代理商: TAS5026APAGR
Architecture Overview
11
SLES068A—February 2003—Revised January 2004
TAS5026A
2.1.6 DCLK
DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The TAS5026A
uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode,
4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I2C addressable
registers, DCLK clock cycles are used to specify interchannel delay and to detect when the MCLK frequency
is drifting. Table 24 DCLK shows the relationship between Sample Rate, MCLK, and DCLK.
Table 24. DCLK
Fs
(kHz)
MCLK
(MHz)
DCLK
(MHz)
DCLK Period
(ns)
32
8.1920
65.5360
15.3
44.1
11.2896
90.3168
11.1
48
12.2880
98.3040
10.2
88
22.5280
90.1120
11.1
96
24.5760
98.3040
10.2
192
49.1520
98.3040
10.2
2.1.7 Serial Data Interface
The TAS5026A operates as a slave only/receive only serial data interface in all modes. The TAS5026A has
three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs.
The serial audio data is in MSB first; 2s complement format.
The serial data interfaces of the TAS5026A can be configured in right justified, I2S, left-justified, or DSP modes.
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register. The supported word
lengths are shown in Table 25.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
Table 25. Supported Word Lengths
DATA MODES
WORD
LENGTHS
MOD2
MOD1
MOD0
Right justified, MSB first
16
0
Right justified, MSB first
20
0
1
Right justified, MSB first
24
0
1
0
I2S
16
0
1
I2S
20
1
0
I2S
24
1
0
1
Left justified, MSB first
24
1
0
DSP frame
16
1
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