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| 型号： | TAS5026APAGRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 6/64页 |
| 文件大小： | 936K |
| 代理商： | TAS5026APAGRG4 |
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Architecture Overview
8
SLES068A—February 2003—Revised January 2004
TAS5026A
If the master clock input can encounter a high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET should be applied during this time There are two recommended control procedures
for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These
control sequences are shown in Section 4.
Table 21. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
DBSPD TERMINAL OR
CONTROL REGISTER BIT
MODE
SPEED SELECTION
0
Master or slave
Normal speed
0
1
Master or slave
Double speed
1
0
Master or slave
Quad speed
0
Slave
Quad speed if MCLK_IN = 128 Fs
1
Master or slave
Error
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs:
Following a RESET when M_S terminal has a logic high applied
The transition to slave mode occurs:
Following a RESET when M_S terminal has a logic low applied
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5026A provides the master clock, SCLK, and LRCLK to the rest
of the system. In the master mode, the TAS5026A outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5026A device generates these clocks plus its internal clocks from the internal phase-locked loop
(PLL). The reference clock for the PLL can be provided by either an external clock source (attached to
XTAL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached
to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the
data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master
mode. The LRCLK frequency is the data sample rate.
2.1.3.1
Crystal Type and Circuit
In clock master mode the TAS5026A can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5026A uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5026A
as shown in Figure 21.
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PDF描述 |
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| TAS5026CPAG | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
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| TAS5026PAG | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TAS5026PAGG4 | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TAS5026CPAG | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5026IPAG | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGG4 | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGR | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGRG4 | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
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