参数资料
型号: TAS5028APAG
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 59/82页
文件大小: 1347K
代理商: TAS5028APAG
Serial Control Interface Register Definitions
57
SLES120 September 2004
TAS5028A
6.11 Automute PWM Threshold and Backend Reset Period (0x15)
Table 611. Automute PWM Threshold and Backend Reset Period
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Set PWM automute threshold equals input automute threshold
0
1
Set PWM automute threshold 1 bit more than input automute threshold
0
1
0
Set PWM automute threshold 2 bits more than input automute threshold
0
1
Set PWM automute threshold 3 bits more than input automute threshold
0
1
0
Set PWM automute threshold 4 bits more than input automute threshold
0
1
0
1
Set PWM automute threshold 5 bits more than input automute threshold
0
1
0
Set PWM automute threshold 6 bits more than input automute threshold
0
1
Set PWM automute threshold 7 bits more than input automute threshold
1
0
Set PWM automute threshold equals input automute threshold
1
0
1
Set PWM automute threshold 1 bit less than input automute threshold
1
0
1
0
Set PWM automute threshold 2 bits less than input automute threshold
1
0
1
Set PWM automute threshold 3 bits less than input automute threshold
1
0
Set PWM automute threshold 4 bits less than input automute threshold
1
0
1
Set PWM automute threshold 5 bits less than input automute threshold
1
0
Set PWM automute threshold 6 bits less than input automute threshold
1
Set PWM automute threshold 7 bits less than input automute threshold
0
Set backend reset period < 1 ms
0
1
Set backend reset period 1 ms
0
1
0
Set backend reset period 2 ms
0
1
Set backend reset period 3 ms
0
1
0
Set backend reset period 4 ms
0
1
0
1
Set backend reset period 5 ms
0
1
0
Set backend reset period 6 ms
0
1
Set backend reset period 7 ms
1
0
Set backend reset period 8 ms
1
0
1
Set backend reset period 9 ms
1
0
1
0
Set backend reset period 10 ms
1
0
1
Set backend reset period 10 ms
1
X
Set backend reset period 10 ms
6.12 Modulation Index Limit Register (0x16)
Table 612. Modulation Index Limit Register
D7
D6
D5
D4
D3
D2
D1
D0
LIMIT
[DCLKS]
MIN WIDTH
[DCLKS]
MODULATION INDEX
0
1
2
99.2%
0
1
2
4
98.4%
0
1
0
3
6
97.7%
0
1
4
8
96.9%
1
0
5
10
96.1%
1
0
1
6
12
95.3%
1
0
7
14
94.5%
1
8
16
93.8%
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