参数资料
型号: TAS5028PAGRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 35/86页
文件大小: 1201K
代理商: TAS5028PAGRG4
TAS5028 Controls and Status
32
SLES112 — June 2004
TAS5028
This delay is generated in the PWM and can be changed at any time through the serial control interface I2C
registers 0x1B – 0x22. The absolute offset for channel 1 is set in I2C sub-address 0x23.
NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a
pure path digital amplifier system. The setting is based upon the type of backend power device
that is used and the layout. These values are set during initialization using the I2C serial
interface. Unless otherwise noted, use the default values given in Table 2 - 9.
2.4
Master Clock and Serial Data Rate Controls
The TAS5028 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right
clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal
allows the TAS5028 to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5028 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5028 accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than
±10 MCLK cycles since the last RESET, the TAS5028 performs
a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
MCLK Ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) - I2C parameter
Data Rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz - I2C parameter
AM Mode Enable / Disable - I2C parameter
During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:
Tuned AM Frequency (for AM interference avoidance) (550 - 1750 kHz) - I2C parameter
Frequency Set Select (1 - 4) - I2C parameter
Sample Rate - I2C parameter or auto detected
2.4.1 PLL Operation
The TAS5028 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL
(DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital
PLL provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal
provides the input reference clock for the digital PLL. The crystal provides a time base to support a number
of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal
time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5028 can receive and store I2C commands and provide status.
2.5
Bank Controls
The TAS5028 permits the user to specify and assign sample rate dependent parameters for Tone in one of
three banks that can be manually selected or selected automatically based upon the data sample rate. Each
bank can be enabled for one or more specific sample rates via I2C bank control register 0x40. Each bank set
holds the following values:
Five Bass Filter-Set Selections (Register 0xDA)
Five Treble Filter-Set Selections (Register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used,
Bank 2 and Bank 3 must be programmed on power- up since the default values are all zeroes. If bank switching
is used and Bank 2 and Bank 3 are not programmed correctly, then the output of the TAS5028 could be muted
when switching to those banks.
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