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参数资料
| 型号： | TAS5028PAGRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 50/86页 |
| 文件大小： | 1201K |
| 代理商： | TAS5028PAGRG4 |
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I2C Serial Control Interface (Slave Address 0x36)
46
SLES112 — June 2004
TAS5028
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5028 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed
by data for that subaddress and the fifteen subaddresses that follow, a sequential I2C write transaction has
taken place, and the data for all 16 subaddresses is successfully received by the TAS5028. For I2C sequential
write transactions, the subaddress then serves as the start address and the amount of data subsequently
transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true
for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a
partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However,
all other data written is accepted; just the incomplete data is discarded.
4.3
Single Byte Write
As shown in Figure 4 - 2, a single byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction
of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the TAS5028 device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5028 internal memory address being accessed.
After receiving the address byte, the TAS5028 again responds with an acknowledge bit. Next, the master
device transmits the data byte to be written to the memory address being accessed. After receiving the data
byte, the TAS5028 again responds with an acknowledge bit. Finally, the master device transmits a stop
condition to complete the single byte data write transfer.
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Sub-Address
Data Byte
Figure 4 - 2. Single Byte Write Transfer
4.4
Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes
are transmitted by the master device to TAS5028 as shown in Figure 4 - 3. After receiving each data byte, the
TAS5028 responds with an acknowledge bit.
D7
D0 ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Sub-Address
Last Data Byte
A6
A5
A1
A0
R/W ACK A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
First Data Byte
A4
A3
A6
Other Data Bytes
ACK
Acknowledge
D0
D7
D0
Figure 4 - 3. Multiple Byte Write Transfer
4.5
Incremental Multiple Byte Write
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte, ... etc., write
operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes
of data. This permits the system to incrementally write large register values without blocking other I2C
transactions.
This feature is enabled by the append subaddress function in the TAS5028. This function enables the
TAS5028 to append 4 bytes of data to a register that was opened by a previous I2C register write operation
but has not received its complete number of data bytes. Since the length of the long registers is a multiple of
4 bytes, using 4-byte transfers will have only an integer number of append operations.
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