List of Illustrations
4
November 2002
SLES044B
5.1
Absolute Maximum Ratings Over Operat-
ing Temperature Ranges . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions (Fs
= 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Electrical Characteristics Over Recom-
mended Operating Conditions . . . . . . . . .
5.3.1
Static Digital Specifications
Over Recommended Operat-
ing Conditions . . . . . . . . . . . . .
5.3.2
Digital Interpolation Filter and
PWM Modulator Over Recom-
mended Operating Conditions
Fs = 48 kHz . . . . . . . . . . . . . . .
5.3.3
TAS5036/TAS5100 System
Performance Measured at the
Speaker Terminals Over
Recommended Operating
Conditions . . . . . . . . . . . . . . . . .
5.4
Switching Characteristics . . . . . . . . . . . . .
5.4.1
Command Sequence Timing .
5.4.2
Serial Audio Port . . . . . . . . . . .
5.4.3
Serial Control Port—I2C Op-
eration . . . . . . . . . . . . . . . . . . . .
6
Application Information . . . . . . . . . . . . . . . . . . . .
6.1
Serial Audio Interface Clock Master and
Slave Interface Configuration . . . . . . . . . .
39
6.1.1
Slave Configuration . . . . . . . . .
6.1.2
Master Configuration . . . . . . .
Appendix A—Volume Table . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Figure
Title
Page
2–1 Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 External PLL Loop Filter . . . . . . . . . . . . . . . . . . . .
2–3 I2S 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 I2S 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Left-Justified 64-Fs Format . . . . . . . . . . . . . . . . . .
2–6 Left-Justified 48-Fs Format . . . . . . . . . . . . . . . . . .
2–7 Right-Justified 64-Fs Format . . . . . . . . . . . . . . . . .
2–8 Right-Justified 48-Fs Format . . . . . . . . . . . . . . . . .
2–9 DSP Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Attenuation Curve . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 De-Emphasis Filter Characteristics . . . . . . . . . .
2–12 PWM Outputs and H-Bridge Driven in BTL
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–13 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . .
2–14 Single Byte Write Transfer . . . . . . . . . . . . . . . . .
2–15 Multiple Byte Write Transfer . . . . . . . . . . . . . . . .
2–16 Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . .
2–17 Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . .
4–1 RESET During System Initialization . . . . . . . . . . .
5–1 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Power-Down and Power-Up Timing—RESET
Preceding PDN . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Power-Down and Power-Up Timing—RESET
Following PDN . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . .