List of Tables
5
November 2002
SLES044B
5–5 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Right-Justified, IIS, Left-Justified Serial Protocol
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Right, Left, and IIS Serial Mode Timing
Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Serial Audio Ports Master Mode Timing . . . . . . .
5–9 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . .
5–10 DSP Serial Port Expanded Timing . . . . . . . . . . .
5–11 DSP Absolute Timing . . . . . . . . . . . . . . . . . . . . . .
5–12 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . .
5–13 Start and Stop Conditions Timing . . . . . . . . . . . .
6–1 Typical TAS5036 Application . . . . . . . . . . . . . . . . .
6–2 TAS5036 Serial Audio Port—Slave Mode
Connection Diagram . . . . . . . . . . . . . . . . . . . . .
6–3 TAS5036 Serial Audio Port—Master Mode
Connection Diagram . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table
Title
Page
2–1 Normal-Speed, Double-Speed, and Quad-Speed
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Master and Slave Clock Modes . . . . . . . . . . . . . .
2–3 LRCLK, MCLK_IN, and External PLL Rates . . .
2–4 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Supported Word Lengths . . . . . . . . . . . . . . . . . . . .
2–6 Device Outputs During Reset . . . . . . . . . . . . . . . .
2–7 Values Set During Reset . . . . . . . . . . . . . . . . . . . .
2–8 Device Outputs During Power Down . . . . . . . . . .
2–9 Volume Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 De-Emphasis Filter Characteristics . . . . . . . . . .
2–11 Device Outputs During Error Recovery . . . . . . .
3–1 I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 General Status Register (Read Only) . . . . . . . . .
3–3 Error Status Register . . . . . . . . . . . . . . . . . . . . . . .
3–4 System Control Register 0 . . . . . . . . . . . . . . . . . .
3–5 System Control Register 1 . . . . . . . . . . . . . . . . . .
3–6 Error Recovery Register . . . . . . . . . . . . . . . . . . . .
3–7 Automute Delay Register . . . . . . . . . . . . . . . . . . . .
3–8 DC-Offset Control Registers . . . . . . . . . . . . . . . . .
3–9 Six Inter-Channel Delay Registers . . . . . . . . . . . .
3–10 ABD Delay Register . . . . . . . . . . . . . . . . . . . . . . .
3–11 Individual Channel Mute Register . . . . . . . . . . . .