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参数资料
| 型号： | TAS5086DBTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封装： | GREEN, TSSOP-38 |
| 文件页数： | 2/47页 |
| 文件大小： | 814K |
| 代理商： | TAS5086DBTG4 |
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DETAILED DESCRIPTION
POWER SUPPLY
CLOCK, ERROR RATE DETECTION, AND PLL
OSCILLATOR TRIM
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
The TAS5086 power-supply section contains regulators that provide analog and digital regulated power for
various sections of the TAS5086. The analog supply supports the analog PLL while digital supplies support the
digital PLL, the digital audio processor, the pulse width modulator, and the output control (reclocker). The
power-supply section is enabled via VREG_EN.
This module provides the timing and serial data interface for the TAS5086.
The TAS5086 is a clock slave device. It accepts MCLK, SCLK, and LRCLK.
The TAS5086 supports 64-fS MCLK for the 176.4-kHz and 192-kHz data rates.
The TAS5086 accepts a 64-fS SCLK rate for all MCLK ratios and a 48-fS SCLK rate for MCLK ratios of 192 fS
and 384 fS.
TAS5086 checks to verify that SCLK is a specific value of 64 fS or 48 fS.
The TAS5086 supports a 1-fS LRCLK.
The timing relationship of these clocks to SDIN[1:4] and SDOUT is shown in subsequent sections.
The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce a
196-MHz PLL output.
The TAS5086 can auto-detect and set the internal clock control logic to the appropriate settings for the
frequencies of 32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed
(176.4 kHz or 192 kHz). The automatic sample rate detection can be disabled and the values set via I2C.
The TAS5086 also supports an AM interference-avoidance mode during which the clock rate is adjusted, in
concert with the PWM sample rate converter, to produce a PWM output at 7-fS, 8-fS, or 9-fS.
The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.
The TAS5086 uses an internal oscillator time base to provide reference timing information for the following
functions:
MCLK, SCLK, and LRCLK error detection
I2C communication when power is first applied to the device
Automatic data-rate detection and setting (32 kHz, normal, double, and quad speed)
Automatic MCLK rate detection and setting (64, 128, 192, 256, 384, and 512 f
S)
The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost
because an external reference is not required. After each power up or reset, a oscillator trim is needed; see the
Oscillator Trim Register (0x1B) section for a detailed procedure.
10
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5086
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相关代理商/技术参数 |
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| TAS5086DBTR | 功能描述:音频 DSP 6 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS5086DBTRG4 | 功能描述:音频 DSP 6 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS5100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRUE DIGITAL AUDIO AMPLIFIER TAS5100A PWM POWER OUTPUT STAGE |
| TAS5100A | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRUE DIGITAL AUDIO AMPLIFIER TAS5100A PWM POWER OUTPUT STAGE |
| TAS5100A_07 | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRUE DIGITAL AUDIO AMPLIFIER TAS5100A PWM POWER OUTPUT STAGE |
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